| Line 6... |
Line 6... |
entity datapath is
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entity datapath is
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port ( clock: in std_logic;
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port ( clock: in std_logic;
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reset: in std_logic;
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reset: in std_logic;
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stall: in std_logic;
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stall: in std_logic;
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busy: in std_logic;
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irq_vector: in std_logic_vector(31 downto 0);
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irq_vector: in std_logic_vector(31 downto 0);
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irq: in std_logic;
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irq: in std_logic;
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irq_ack: out std_logic;
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irq_ack: out std_logic;
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inst_addr: out std_logic_vector(31 downto 0);
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address: out std_logic_vector(31 downto 0);
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inst_in: in std_logic_vector(31 downto 0);
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data_addr: out std_logic_vector(31 downto 0);
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data_in: in std_logic_vector(31 downto 0);
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data_in: in std_logic_vector(31 downto 0);
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data_out: out std_logic_vector(31 downto 0);
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data_out: out std_logic_vector(31 downto 0);
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data_w: out std_logic_vector(3 downto 0);
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data_w: out std_logic_vector(3 downto 0);
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data_access: out std_logic
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data_access: out std_logic
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);
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);
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| Line 30... |
Line 26... |
signal data_in_s, pc, pc_last, pc_plus4, pc_next, result, branch, jump, ext32, ext32b, ext32h, alu_src: std_logic_vector(31 downto 0);
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signal data_in_s, pc, pc_last, pc_plus4, pc_next, result, branch, jump, ext32, ext32b, ext32h, alu_src: std_logic_vector(31 downto 0);
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signal opcode, funct: std_logic_vector(5 downto 0);
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signal opcode, funct: std_logic_vector(5 downto 0);
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signal read_reg1, read_reg2, write_reg, rs, rt, rd, target: std_logic_vector(4 downto 0);
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signal read_reg1, read_reg2, write_reg, rs, rt, rd, target: std_logic_vector(4 downto 0);
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signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);
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signal write_data, read_data1, read_data2: std_logic_vector(31 downto 0);
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signal imm: std_logic_vector(15 downto 0);
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signal imm: std_logic_vector(15 downto 0);
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signal wreg, zero, less_than, br_link_ctl, branch_taken, jump_taken, stall_reg: std_logic;
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signal wreg, zero, less_than, br_link_ctl, branch_taken, jump_taken, mwait, stall_reg: std_logic;
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signal irq_ack_s, irq_ack_s_dly, bds: std_logic;
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signal irq_ack_s, irq_ack_s_dly, bds, data_access_s, data_access_s_dly: std_logic;
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-- control signals
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-- control signals
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signal reg_dst_ctl, reg_write_ctl, alu_src_ctl, reg_to_mem_ctl, mem_to_reg_ctl, mem_to_reg_ctl_dly, signed_imm_ctl, signed_rd_ctl, shift_ctl: std_logic;
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signal reg_dst_ctl, reg_write_ctl, alu_src_ctl, reg_to_mem_ctl, mem_to_reg_ctl, mem_to_reg_ctl_dly, signed_imm_ctl, signed_rd_ctl, shift_ctl: std_logic;
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signal jump_ctl, mem_read_ctl, mem_write_ctl: std_logic_vector(1 downto 0);
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signal jump_ctl, mem_read_ctl, mem_write_ctl: std_logic_vector(1 downto 0);
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signal branch_ctl: std_logic_vector(2 downto 0);
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signal branch_ctl: std_logic_vector(2 downto 0);
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| Line 54... |
Line 50... |
-- FETCH STAGE
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-- FETCH STAGE
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--
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--
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-- 1st stage, instruction memory access, PC update, interrupt acknowledge logic
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-- 1st stage, instruction memory access, PC update, interrupt acknowledge logic
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-- program counter logic
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-- program counter logic
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process(clock, reset, reg_to_mem_ctl_r, mem_to_reg_ctl_r, busy, stall)
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process(clock, reset, reg_to_mem_ctl_r, mem_to_reg_ctl_r, mwait, stall)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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pc <= (others => '0');
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pc <= (others => '0');
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pc_last <= (others => '0');
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pc_last <= (others => '0');
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elsif clock'event and clock = '1' then
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elsif clock'event and clock = '1' then
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if stall = '0' then
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if stall = '0' then
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if busy = '0' then
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if mwait = '0' then
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pc <= pc_next;
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pc <= pc_next;
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pc_last <= pc;
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pc_last <= pc;
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else
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else
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if (reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1') and bds = '0' then
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if (reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1') and bds = '0' then
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pc <= pc_last;
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pc <= pc_last;
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| Line 87... |
Line 83... |
bds = '0' and branch_taken = '0' and jump_taken = '0' and
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bds = '0' and branch_taken = '0' and jump_taken = '0' and
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reg_to_mem_ctl_r = '0' and mem_to_reg_ctl_r = '0' else '0';
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reg_to_mem_ctl_r = '0' and mem_to_reg_ctl_r = '0' else '0';
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irq_ack <= irq_ack_s_dly;
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irq_ack <= irq_ack_s_dly;
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process(clock, reset, irq, irq_ack_s, mem_to_reg_ctl_r, busy, stall)
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process(clock, reset, irq, irq_ack_s, mem_to_reg_ctl_r, mwait, stall)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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irq_ack_s_dly <= '0';
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irq_ack_s_dly <= '0';
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bds <= '0';
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bds <= '0';
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mem_to_reg_ctl_dly <= '0';
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mem_to_reg_ctl_dly <= '0';
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stall_reg <= '0';
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stall_reg <= '0';
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data_access_s_dly <= '0';
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elsif clock'event and clock = '1' then
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elsif clock'event and clock = '1' then
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stall_reg <= stall;
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stall_reg <= stall;
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if stall = '0' then
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if stall = '0' then
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mem_to_reg_ctl_dly <= mem_to_reg_ctl_r;
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mem_to_reg_ctl_dly <= mem_to_reg_ctl_r;
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if busy = '0' then
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data_access_s_dly <= data_access_s;
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if mwait = '0' then
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irq_ack_s_dly <= irq_ack_s;
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irq_ack_s_dly <= irq_ack_s;
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if branch_taken = '1' or jump_taken = '1' then
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if branch_taken = '1' or jump_taken = '1' then
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bds <= '1';
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bds <= '1';
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else
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else
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bds <= '0';
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bds <= '0';
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| Line 116... |
Line 114... |
-- DECODE STAGE
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-- DECODE STAGE
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--
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--
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-- 2nd stage, instruction decode, control unit operation, pipeline bubble insertion logic on load/store and 2nd branch delay slot
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-- 2nd stage, instruction decode, control unit operation, pipeline bubble insertion logic on load/store and 2nd branch delay slot
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-- instruction decode
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-- instruction decode
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opcode <= inst_in(31 downto 26);
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opcode <= data_in(31 downto 26);
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rs <= inst_in(25 downto 21);
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rs <= data_in(25 downto 21);
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rt <= inst_in(20 downto 16);
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rt <= data_in(20 downto 16);
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rd <= "11111" when br_link_ctl = '1' else inst_in(15 downto 11); -- FIXME: this will not work for the 'jalr rd, rs' format
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rd <= "11111" when br_link_ctl = '1' else data_in(15 downto 11); -- FIXME: this will not work for the 'jalr rd, rs' format
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funct <= inst_in(5 downto 0);
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funct <= data_in(5 downto 0);
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imm <= inst_in(15 downto 0);
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imm <= data_in(15 downto 0);
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-- control unit
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-- control unit
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control_hellfire: entity work.control
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control_unit: entity work.control
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port map( opcode => opcode,
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port map( opcode => opcode,
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funct => funct,
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funct => funct,
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rtx => rt,
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rtx => rt,
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reg_dst => reg_dst_ctl,
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reg_dst => reg_dst_ctl,
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reg_write => reg_write_ctl,
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reg_write => reg_write_ctl,
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| Line 144... |
Line 142... |
mem_read => mem_read_ctl,
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mem_read => mem_read_ctl,
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signed_rd => signed_rd_ctl,
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signed_rd => signed_rd_ctl,
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shift => shift_ctl
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shift => shift_ctl
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);
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);
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process(clock, reset, busy, stall)
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process(clock, reset, mwait, stall)
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begin
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begin
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if reset = '1' then
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if reset = '1' then
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rs_r <= (others => '0');
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rs_r <= (others => '0');
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rt_r <= (others => '0');
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rt_r <= (others => '0');
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rd_r <= (others => '0');
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rd_r <= (others => '0');
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| Line 187... |
Line 185... |
mem_write_ctl_r <= "00";
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mem_write_ctl_r <= "00";
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mem_read_ctl_r <= "00";
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mem_read_ctl_r <= "00";
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signed_rd_ctl_r <= '0';
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signed_rd_ctl_r <= '0';
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shift_ctl_r <= '0';
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shift_ctl_r <= '0';
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else
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else
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if busy = '0' then
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if mwait = '0' then
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if reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1' or bds = '1' then
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if reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1' or bds = '1' then
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rs_r <= (others => '0');
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rs_r <= (others => '0');
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rt_r <= (others => '0');
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rt_r <= (others => '0');
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rd_r <= (others => '0');
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rd_r <= (others => '0');
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imm_r <= (others => '0');
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imm_r <= (others => '0');
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| Line 257... |
Line 255... |
read_reg2 <= "00000" when branch_ctl_r > "010" else -- source for branch and link (for zero operations)
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read_reg2 <= "00000" when branch_ctl_r > "010" else -- source for branch and link (for zero operations)
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rs_r when shift_ctl_r = '1' else rt_r; -- source for register based shifts or normal operations
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rs_r when shift_ctl_r = '1' else rt_r; -- source for register based shifts or normal operations
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write_reg <= target when mem_to_reg_ctl_r = '0' else rt_r;
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write_reg <= target when mem_to_reg_ctl_r = '0' else rt_r;
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ext32 <= x"0000" & imm_r when (imm_r(15) = '0' or signed_imm_ctl_r = '0') else x"ffff" & imm_r;
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ext32 <= x"0000" & imm_r when (imm_r(15) = '0' or signed_imm_ctl_r = '0') else x"ffff" & imm_r;
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target <= rt_r when reg_dst_ctl_r = '0' else rd_r; -- target register selection
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target <= rt_r when reg_dst_ctl_r = '0' else rd_r; -- target register selection
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wreg <= (reg_write_ctl_r or mem_to_reg_ctl_dly) and not busy and not stall_reg; -- enable the register bank for write back also
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wreg <= (reg_write_ctl_r or mem_to_reg_ctl_dly) and not mwait and not stall_reg; -- enable the register bank for write back also
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-- 3rd stage (b) ALU operation
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-- 3rd stage (b) ALU operation
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alu: entity work.alu
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alu: entity work.alu
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port map( op1 => read_data1,
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port map( op1 => read_data1,
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op2 => alu_src,
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op2 => alu_src,
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| Line 283... |
Line 281... |
((zero = '0' and less_than = '1') and branch_ctl_r = "101") or -- BLTZ, BLTZAL
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((zero = '0' and less_than = '1') and branch_ctl_r = "101") or -- BLTZ, BLTZAL
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((zero = '1' or less_than = '0') and branch_ctl_r = "110") -- BGEZ, BGEZAL
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((zero = '1' or less_than = '0') and branch_ctl_r = "110") -- BGEZ, BGEZAL
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else '0';
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else '0';
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jump_taken <= '1' when jump_ctl_r /= "00" else '0'; -- J, JAL, JR, JALR
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jump_taken <= '1' when jump_ctl_r /= "00" else '0'; -- J, JAL, JR, JALR
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inst_addr <= pc;
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address <= result when data_access_s = '1' and mwait = '1' else pc;
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data_addr <= result; --result(31 downto 2) & "00";
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data_access_s <= '1' when reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1' else '0';
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data_access <= '1' when reg_to_mem_ctl_r = '1' or mem_to_reg_ctl_r = '1' else '0';
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mwait <= '1' when data_access_s = '1' and data_access_s_dly = '0' else '0';
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data_access <= mwait;
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-- 3rd stage (c) data memory / write back operation, register file access (write)
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-- 3rd stage (c) data memory / write back operation, register file access (write)
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-- memory access, store operations
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-- memory access, store operations
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process(mem_write_ctl_r, result, read_data2)
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process(mem_write_ctl_r, result, read_data2)
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