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-- HF-RISCV v1.2
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-- HF-RISCV v1.3
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-- Sergio Johann Filho, 2015 - 2016
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-- Sergio Johann Filho, 2015 - 2016
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--
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--
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-- *This is a quick and dirty organization of a 3-stage pipelined RISC-V microprocessor. All registers / memory
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-- *This is a quick and dirty organization of a 3-stage pipelined RISC-V microprocessor. All registers / memory
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-- accesses are synchronized to the rising edge of clock. The same processor could be designed with only 2
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-- accesses are synchronized to the rising edge of clock. The same processor could be designed with only 2
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-- pipeline stages, but this would require memories to be either asynchronous (as presented on comp arq text
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-- pipeline stages, but this would require memories to be either asynchronous (as presented on comp arq text
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signal compare2_reg: std_logic_vector(23 downto 0);
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signal compare2_reg: std_logic_vector(23 downto 0);
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signal interrupt, irq, irq_counter, irq_counter_not, irq_counter2, irq_counter2_not, irq_compare, irq_compare2, compare_trig, compare2_trig: std_logic;
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signal interrupt, irq, irq_counter, irq_counter_not, irq_counter2, irq_counter2_not, irq_compare, irq_compare2, compare_trig, compare2_trig: std_logic;
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signal data_read_uart, data_write_uart: std_logic_vector(7 downto 0);
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signal data_read_uart, data_write_uart: std_logic_vector(7 downto 0);
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signal enable_uart, enable_uart_read, enable_uart_write, uart_write_busy, uart_data_avail: std_logic;
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signal enable_uart, enable_uart_read, enable_uart_write, uart_write_busy, uart_data_avail: std_logic;
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type pulse_state_type is (irq_idle, irq_intdly1, irq_intdly2, irq_int, irq_req, irq_ackn, irq_done);
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type pulse_state_type is (irq_idle, irq_int, irq_req, irq_ackn, irq_done);
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signal pulse_state: pulse_state_type;
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signal pulse_state: pulse_state_type;
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signal pulse_next_state: pulse_state_type;
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signal pulse_next_state: pulse_state_type;
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signal periph_access, periph_access_we, data_access_cpu_dly, data_access_cpu_dly2: std_logic;
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signal periph_access, periph_access_we, data_access_cpu_dly, data_access_cpu_dly2: std_logic;
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signal data_we_mem_s: std_logic_vector(3 downto 0);
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signal data_we_mem_s: std_logic_vector(3 downto 0);
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compare_trig <= '1';
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compare_trig <= '1';
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end if;
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end if;
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if compare2_reg = counter_reg(23 downto 0) then
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if compare2_reg = counter_reg(23 downto 0) then
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compare2_trig <= '1';
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compare2_trig <= '1';
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end if;
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end if;
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if irq = '0' and exception_cpu = '0' then
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if periph_access = '1' and periph_access_we = '1' then
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if periph_access = '1' and periph_access_we = '1' then
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case data_addr_cpu(7 downto 4) is
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case data_addr_cpu(7 downto 4) is
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when "0000" => -- IRQ_VECTOR
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when "0000" => -- IRQ_VECTOR
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irq_vector_reg <= data_out_cpu(7 downto 0) & data_out_cpu(15 downto 8) & data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
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irq_vector_reg <= data_out_cpu(7 downto 0) & data_out_cpu(15 downto 8) & data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
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when "0010" => -- IRQ_MASK
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when "0010" => -- IRQ_MASK
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when "1111" => -- UART_DIVISOR
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when "1111" => -- UART_DIVISOR
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uart_divisor <= data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
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uart_divisor <= data_out_cpu(23 downto 16) & data_out_cpu(31 downto 24);
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when others =>
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when others =>
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end case;
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end case;
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end if;
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end if;
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else
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if irq_ack_cpu = '1' or exception_cpu = '1' then
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irq_status_reg(0) <= '0'; -- IRQ_STATUS (clear master int bit on interrupt)
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irq_status_reg(0) <= '0'; -- IRQ_STATUS (clear master int bit on interrupt)
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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elsif clock'event and clock = '1' then
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elsif clock'event and clock = '1' then
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if stall = '0' then
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if stall = '0' then
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pulse_state <= pulse_next_state;
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pulse_state <= pulse_next_state;
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case pulse_state is
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case pulse_state is
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when irq_idle =>
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when irq_idle =>
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if interrupt = '1' then
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if interrupt = '1' and irq_status_reg(0) = '1' then
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pulse_next_state <= irq_intdly1;
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end if;
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when irq_intdly1 =>
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if irq_status_reg(0) = '1' then
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pulse_next_state <= irq_intdly2;
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end if;
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when irq_intdly2 =>
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pulse_next_state <= irq_int;
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pulse_next_state <= irq_int;
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end if;
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when irq_int =>
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when irq_int =>
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irq <= '1';
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irq <= '1';
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pulse_next_state <= irq_req;
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pulse_next_state <= irq_req;
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when irq_req =>
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when irq_req =>
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if irq_ack_cpu = '1' then
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if irq_ack_cpu = '1' then
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