| Line 30... |
Line 30... |
`include "defines.v"
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`include "defines.v"
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module accumulator (
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module accumulator (
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input rst,
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input rst,
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input ap, bp, dp,
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input ap, bp, dp,
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input dx, d0, d1, d2, d3, d4, d5, d6, d7, d8, d9, d10,
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input d1, d2, d10,
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input dxu, d0u, d1l,
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input dxu, d0u,
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input wu, wl,
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input wu, wl,
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input [0:6] adder_out,
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input [0:6] adder_out,
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input acc_regen_gate, right_shift_gate, acc_ri_gate,
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input acc_regen_gate, right_shift_gate, acc_ri_gate,
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zero_shift_count, man_acc_reset, reset_op_latch,
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zero_shift_count, man_acc_reset, reset_op_latch,
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input [0:3] early_idx, ontime_idx,
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input [0:3] early_idx, ontime_idx,
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| Line 53... |
Line 53... |
//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// A -- Read into early_out from RAM
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// A -- Read into early_out from RAM
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// Read into ontime_out
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// Read into ontime_out
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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wire acc_reset = reset_op_latch | man_acc_reset
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wire acc_reset = reset_op_latch | man_acc_reset
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| (zero_shift_count & wl & (d1l | d2));
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| (zero_shift_count & wl & (d1 | d2));
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always @(posedge ap) begin
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always @(posedge ap) begin
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if (rst) begin
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if (rst) begin
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early_out <= `biq_blank;
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early_out <= `biq_blank;
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ontime_out <= `biq_blank;
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ontime_out <= `biq_blank;
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end else begin
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end else begin
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