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`include "defines.v"
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`include "defines.v"
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module accumulator (
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module accumulator (
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input rst,
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input rst,
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input ap, bp, dp,
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input ap, bp, dp,
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input d1, d2, d10,
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input dx, d1, d2, d10,
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input dxu, d0u,
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input dxu, d0u,
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input wu, wl,
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input wu, wl,
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input [0:6] adder_out,
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input [0:6] adder_out,
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input acc_regen_gate, right_shift_gate, acc_ri_gate,
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input acc_regen_gate, right_shift_gate, acc_ri_gate,
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zero_shift_count, man_acc_reset, reset_op_latch,
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zero_shift_count, man_acc_reset, reset_op_latch,
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// The accumulator occupies 22 locations of a 32x7bit RAM.
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// The accumulator occupies 22 locations of a 32x7bit RAM.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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reg [0:6] digits [0:31];
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reg [0:6] digits [0:31];
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wire [0:4] acc_early_idx = {(d10? ~wu : wu), early_idx};
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wire [0:4] acc_early_idx = {(dx? ~wu : wu), early_idx};
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wire [0:4] acc_ontime_idx = {wu, ontime_idx};
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wire [0:4] acc_ontime_idx = {wu, ontime_idx};
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// A -- Read into early_out from RAM
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// A -- Read into early_out from RAM
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// Read into ontime_out
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// Read into ontime_out
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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wire acc_reset = reset_op_latch | man_acc_reset
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wire acc_reset = reset_op_latch | man_acc_reset
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| (zero_shift_count & wl & (d1 | d2));
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| (zero_shift_count & wl & (d1 | d2));
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always @(posedge ap) begin
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always @(posedge ap)
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if (rst) begin
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if (rst) begin
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early_out <= `biq_blank;
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early_out <= `biq_blank;
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ontime_out <= `biq_blank;
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ontime_out <= `biq_blank;
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end else begin
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end else begin
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early_out <= reset_op_latch? `biq_0
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early_out <= reset_op_latch? `biq_0
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: digits[acc_early_idx];
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: digits[acc_early_idx];
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ontime_out <= (acc_reset | d0u | dxu)? `biq_0 : early_out;
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ontime_out <= (acc_reset | d0u | dxu)? `biq_0 : early_out;
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end
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end;
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end;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// B -- Read into ped_out
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// B -- Read into ped_out
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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always @(posedge bp) begin
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always @(posedge bp)
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if (rst) begin
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if (rst) begin
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ped_out <= `biq_blank;
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ped_out <= `biq_blank;
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end else begin
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end else begin
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ped_out <= right_shift_gate? early_out
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ped_out <= right_shift_gate? early_out
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: acc_ri_gate? adder_out
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: acc_ri_gate? adder_out
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: acc_regen_gate? ontime_out
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: acc_regen_gate? ontime_out
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: `biq_blank;
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: `biq_blank;
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end
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end;
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end;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// D -- Write ped_out into RAM
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// D -- Write ped_out into RAM
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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always @(posedge dp) begin
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always @(posedge dp)
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digits[acc_ontime_idx] <= ped_out;
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digits[acc_ontime_idx] <= ped_out;
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end;
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endmodule
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endmodule
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No newline at end of file
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No newline at end of file
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