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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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`include "defines.v"
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`include "defines.v"
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module adder (
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module adder (
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input rst,
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input rst,
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input bp, dp, c_a, edxu, dx, ed0u, d1, ed1l, d10, d10u, wl,
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input ap, bp, dp,
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dxu, dx, d0u, d1, d1l, d10, d10u, wl,
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input [0:6] entry_a, entry_b,
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input [0:6] entry_a, entry_b,
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input tlu_on, left_shift_off, left_shift_on,
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input tlu_on, left_shift_off, left_shift_on,
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input no_carry_insert, no_carry_blank, carry_insert, carry_blank,
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input no_carry_insert, no_carry_blank, carry_insert, carry_blank,
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input zero_insert,
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input zero_insert,
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input quotient_digit_on, overflow_stop_sw, overflow_sense_sw,
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input quotient_digit_on, overflow_stop_sw, overflow_sense_sw,
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input mult_div_off, dist_true_add_gate, acc_true_add_latch,
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input mult_div_off, dist_true_add_gate, acc_true_add_latch,
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input shift_overflow,
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input shift_overflow,
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output reg[0:6] adder_out,
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output reg[0:6] adder_out,
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output reg carry_test, no_carry_test,
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output reg carry_test, no_carry_test, d0l_carry_sig, overflow_stop,
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output d0l_carry_sig,
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output overflow_stop, overflow_light, overflow_sense_sig
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output overflow_light, overflow_sense_sig
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);
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);
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// The 650 adder operates like this:
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// The 650 bi-quinary adder accepts its inputs early (i.e., one clock ahead),
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// The adder output latches are normally reset by AP except when
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// producing a result during the next digit time. This implementation retains
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// suppressed by reset_cntrl. reset_cntrl is turned
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// sum and carries in _hold flip-flops, the 650 used other tricky means.
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// off by (plate pullover):
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// tlu_on | (cp & d1 & lt_sh_on) | (cp & ed0u & lt_sh_off)
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// and on by:
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// (bp & wl & d10 & lt_sh_off) | (bp & edxu & lt_sh_on)
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// The carry and no_carry signals are gated by DP, which
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// in turn gates the adder output. The falling edge of DP triggers
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// the output latches, the pulse lasting past the reset action of
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// AP.
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//
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// Schedule for this implementation:
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// A : --
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// B : Combinational logic begins forming new sum and carry
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// Previous sum and carry brought to adder output
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// Setup reset_cntrl
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// Setup overflow_stop_latch
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// C : --
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// D : Save combinational logic new sum and carry
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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reg [0:6] sum_hold;
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reg [0:6] sum_hold;
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reg carry_hold, no_carry_hold, carry_test_hold, no_carry_test_hold;
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reg carry_hold, no_carry_hold, carry_test_hold, no_carry_test_hold;
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reg reset_cntrl;
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reg reset_ctl;
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reg carry, no_carry;
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reg carry, no_carry;
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reg overflow_stop_latch;
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assign d0l_carry_sig = c_a & wl & dx & carry;
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assign overflow_stop = overflow_stop_latch;
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assign overflow_light = overflow_stop_latch;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Bi-quinary adder, forms biq sum of two biq digits with carry in and out.
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// Bi-quinary adder, forms biq sum of two biq digits with carry in and out.
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// Hand captured from 650 patent fig. 68.
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// Hand captured from 650 patent fig. 68.
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//
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// By design, this logic produces a sum of all zeroes with zero carry_out and
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// no_carry_out whenever entry_a or entry_b or both carry and no_carry are
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// zero.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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wire b0_and_b5 = (entry_a[`biq_b0] & entry_b[`biq_b5])
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wire b0_and_b5 = (entry_a[`biq_b0] & entry_b[`biq_b5])
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| (entry_a[`biq_b5] & entry_b[`biq_b0]);
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| (entry_a[`biq_b5] & entry_b[`biq_b0]);
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wire q4_a_or_b = entry_a[`biq_q4] | entry_b[`biq_q4];
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wire q4_a_or_b = entry_a[`biq_q4] | entry_b[`biq_q4];
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wire q3_a_or_b = entry_a[`biq_q3] | entry_b[`biq_q3];
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wire q3_a_or_b = entry_a[`biq_q3] | entry_b[`biq_q3];
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wire sum_b5 = b5_no_carry | b5_carry;
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wire sum_b5 = b5_no_carry | b5_carry;
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wire [0:6] sum_out = {sum_b5, sum_b0, sum_q4, sum_q3, sum_q2, sum_q1, sum_q0};
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wire [0:6] sum_out = {sum_b5, sum_b0, sum_q4, sum_q3, sum_q2, sum_q1, sum_q0};
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wire carry_out = b0_carry | b5_carry;
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wire carry_out = b0_carry | b5_carry;
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wire no_carry_out = b0_no_carry | b5_no_carry;
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wire no_carry_out = b0_no_carry | b5_no_carry;
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wire overflow = shift_overflow
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| (carry_test & d10u & dist_true_add_gate
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& acc_true_add_latch & mult_div_off);
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assign overflow_sense_sig = overflow & overflow_sense_sw;
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// B --
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// A : Supply sum and carries from previous digit time
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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always @(posedge rst, posedge bp) begin
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always @(posedge ap)
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if (rst) begin
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if (rst) begin
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adder_out <= `biq_blank;
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adder_out <= `biq_blank;
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reset_cntrl <= 0;
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carry_test <= 0;
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carry_test <= 0;
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no_carry_test <= 0;
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no_carry_test <= 0;
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carry <= 0;
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carry <= 0;
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no_carry <= 0;
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no_carry <= 0;
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overflow_stop_latch <= 0;
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end else begin
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end else begin
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adder_out <= sum_hold;
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adder_out <= sum_hold;
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carry_test <= carry_test_hold;
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carry_test <= carry_test_hold;
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no_carry_test <= no_carry_test_hold;
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no_carry_test <= no_carry_test_hold;
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carry <= carry_hold;
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carry <= carry_hold;
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no_carry <= no_carry_hold;
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no_carry <= no_carry_hold;
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if (tlu_on | (d1 & left_shift_on) | (ed0u & left_shift_off)) begin
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reset_cntrl <= 0;
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end else if ((wl & d10 & left_shift_off) | (edxu & left_shift_on)) begin
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reset_cntrl <= 1;
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end
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if (error_reset) begin
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overflow_stop_latch <= 0;
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end else if ((ed1l & carry_test & quotient_digit_on)
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| (overflow & overflow_stop_sw)) begin
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overflow_stop_latch <= 1;
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end
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end
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end
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wire reset_ctl_on_p = (wl & d10 & left_shift_off) | (dxu & left_shift_on);
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wire reset_ctl_off_p = tlu_on | (d1 & left_shift_on) | (d0u & left_shift_off);
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always @(posedge ap)
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if (rst) begin
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reset_ctl <= 0;
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end else if (reset_ctl_on_p) begin
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reset_ctl <= 1;
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end else if (reset_ctl_off_p) begin
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reset_ctl <= 0;
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end;
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wire overflow = shift_overflow
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& acc_true_add_latch & mult_div_off);
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assign overflow_sense_sig = overflow & overflow_sense_sw;
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wire overflow_stop_p = (d1l & carry_test & quotient_digit_on)
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| (overflow & overflow_stop_sw);
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assign overflow_light = overflow_stop;
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always @(posedge bp)
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if (rst) begin
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overflow_stop <= 1;
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end else if (error_reset) begin
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overflow_stop <= 0;
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end else if (overflow_stop_p) begin
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overflow_stop <= 1;
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end;
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end;
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always @(posedge rst, posedge dp) begin
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always @(posedge dp)
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if (rst) d0l_carry_sig <= 0;
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else if (wl & d1) d0l_carry_sig <= 0;
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else if (wl & dx & carry_out) d0l_carry_sig <= 1;
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always @(posedge dp)
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if (rst) begin
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if (rst) begin
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sum_hold <= `biq_blank;
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sum_hold <= `biq_blank;
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carry_hold <= 0;
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carry_hold <= 0;
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no_carry_hold <= 0;
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no_carry_hold <= 0;
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carry_test_hold <= 0;
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carry_test_hold <= 0;
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no_carry_test_hold <= 0;
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no_carry_test_hold <= 0;
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end else begin
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end else begin
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sum_hold <= zero_insert? `biq_0
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sum_hold <= zero_insert? `biq_0
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: reset_cntrl? sum_hold
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: reset_ctl? sum_hold
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: sum_out;
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: sum_out;
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carry_hold <= (reset_cntrl | carry_blank)? 1'b0
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carry_hold <= (reset_ctl | carry_blank)? 1'b0
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: carry_insert? 1'b1
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: carry_insert? 1'b1
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: carry_out;
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: carry_out;
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no_carry_hold <= (reset_cntrl | no_carry_blank)? 1'b0
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no_carry_hold <= (reset_ctl | no_carry_blank)? 1'b0
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: no_carry_insert? 1'b1
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: no_carry_insert? 1'b1
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: no_carry_out;
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: no_carry_out;
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carry_test_hold <= reset_cntrl? 1'b0 : carry_out;
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carry_test_hold <= reset_ctl? 1'b0 : carry_out;
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no_carry_test_hold <= reset_cntrl? 1'b0 : no_carry_out;
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no_carry_test_hold <= reset_ctl? 1'b0 : no_carry_out;
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end
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end;
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end;
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endmodule
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endmodule
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