| Line 54... |
Line 54... |
output reg busy, digit_ready,
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output reg busy, digit_ready,
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output reg punch_card, read_card, card_digit_ready
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output reg punch_card, read_card, card_digit_ready
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);
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);
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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// Operator console switch settings
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// Operator console switch settings and their control signals.
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//-----------------------------------------------------------------------------
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//-----------------------------------------------------------------------------
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reg pgm_sw_stop, pgm_sw_run,
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reg pgm_sw_stop, pgm_sw_run,
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half_cycle_sw_run, half_cycle_sw_half,
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half_cycle_sw_run, half_cycle_sw_half,
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ctl_sw_addr_stop, ctl_sw_run, ctl_sw_manual,
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ctl_sw_addr_stop, ctl_sw_run, ctl_sw_manual,
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disp_sw_lacc, disp_sw_uacc, disp_sw_dist, disp_sw_pgm,
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disp_sw_lacc, disp_sw_uacc, disp_sw_dist, disp_sw_pgm,
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| Line 70... |
Line 70... |
assign half_or_pgm_stop = half_cycle_sw_half | pgm_stop;
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assign half_or_pgm_stop = half_cycle_sw_half | pgm_stop;
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assign ri_storage = disp_sw_ri;
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assign ri_storage = disp_sw_ri;
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assign ro_storage = disp_sw_ro;
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assign ro_storage = disp_sw_ro;
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assign storage_control = run_control | disp_sw_ro;
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assign storage_control = run_control | disp_sw_ro;
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reg do_power_on_reset, do_reset_console, do_err_reset, do_err_sense_reset,
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//-----------------------------------------------------------------------------
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do_pgm_reset, do_acc_reset, do_hard_reset, do_clear_drum;
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// Calculate the RAM address of the general storage word at address gs_addr_.
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reg [0:5] state;
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//-----------------------------------------------------------------------------
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|
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reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
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reg [0:6] gs_addr_th, gs_addr_h, gs_addr_t, gs_addr_u;
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wire [0:14] gs_band_addr;
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wire [0:14] gs_band_addr;
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wire [0:9] gs_word_offset;
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wire [0:9] gs_word_offset;
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ram_band_addr rba(gs_addr_th, gs_addr_h, gs_addr_t, gs_band_addr);
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ram_band_addr rba(gs_addr_th, gs_addr_h, gs_addr_t, gs_band_addr);
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ram_word_offset rwo(gs_addr_t, gs_addr_u, gs_word_offset);
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ram_word_offset rwo(gs_addr_t, gs_addr_u, gs_word_offset);
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wire [0:14] gs_word_addr = gs_band_addr + gs_word_offset;
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wire [0:14] gs_word_addr = gs_band_addr + gs_word_offset;
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//-----------------------------------------------------------------------------
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// Operator console state machine
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//-----------------------------------------------------------------------------
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reg do_power_on_reset, do_reset_console, do_err_reset, do_err_sense_reset,
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do_pgm_reset, do_acc_reset, do_hard_reset, do_clear_drum;
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reg [0:5] state;
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`define state_idle 6'd0
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`define state_idle 6'd0
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`define state_reset_console_1 6'd1
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`define state_reset_console_1 6'd1
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`define state_reset_console_2 6'd2
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`define state_reset_console_2 6'd2
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`define state_pgm_reset_1 6'd3
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`define state_pgm_reset_1 6'd3
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| Line 112... |
Line 118... |
`define state_read_gs_1 6'd30
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`define state_read_gs_1 6'd30
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`define state_read_gs_2 6'd31
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`define state_read_gs_2 6'd31
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`define state_read_gs_3 6'd32
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`define state_read_gs_3 6'd32
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`define state_read_gs_4 6'd33
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`define state_read_gs_4 6'd33
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`define state_read_gs_5 6'd34
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`define state_read_gs_5 6'd34
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`define state_read_gs_6 6'd35
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|
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`define state_clear_drum_1 6'd50
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`define state_clear_drum_1 6'd50
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`define state_clear_drum_2 6'd51
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`define state_clear_drum_2 6'd51
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`define state_clear_drum_3 6'd52
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`define state_clear_drum_3 6'd52
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|
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//-----------------------------------------------------------------------------
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// Operator console state machine
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//-----------------------------------------------------------------------------
|
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (rst) begin
|
if (rst) begin
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console_to_addr <= 0;
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console_to_addr <= 0;
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pgm_start <= 0;
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pgm_start <= 0;
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pgm_stop <= 0;
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pgm_stop <= 0;
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| Line 630... |
Line 634... |
|
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// Read word from general storage
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// Read word from general storage
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// --> 4 digits address, little-endian
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// --> 4 digits address, little-endian
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// <-- 1 digit sign, 10 digits, little-endian
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// <-- 1 digit sign, 10 digits, little-endian
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// 0 : Ignore if CPU not stopped
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// 0 : Ignore if CPU not stopped
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// Accept low-order address digit
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// 1 : Accept first address digit
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// 1 : Accept remaining address digits
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// 2 : Accept remaining address digits
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// 2 : Calculate word origin in gs RAM
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// 2 : Calculate word origin in gs RAM
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// Validate address
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// Validate address
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// console_read_gs <= 1;
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// console_read_gs <= 1;
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// 3 : Send gs-early digit to out
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// 3 : Send gs-early digit to out
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// digit_ready <= 1;
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// digit_ready <= 1;
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| Line 657... |
Line 661... |
digit_ready <= 0;
|
digit_ready <= 0;
|
end
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end
|
end
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end
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|
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`state_read_gs_3: begin
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`state_read_gs_3: begin
|
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if (d10) begin
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gs_ram_addr <= gs_word_addr;
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gs_ram_addr <= gs_word_addr;
|
|
read_gs <= 1;
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state <= `state_read_gs_4;
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state <= `state_read_gs_4;
|
end
|
end
|
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end
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|
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`state_read_gs_4: begin
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`state_read_gs_4: begin
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cmd_digit_out <= gs_in;
|
|
state <= `state_read_gs_5;
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state <= `state_read_gs_5;
|
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gs_ram_addr <= gs_ram_addr + 1;
|
|
end
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|
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`state_read_gs_5: begin
|
|
digit_ready <= 1;
|
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cmd_digit_out <= gs_in;
|
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gs_ram_addr <= gs_ram_addr + 1;
|
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if (dx) begin
|
|
state <= `state_read_gs_6;
|
|
read_gs <= 0;
|
|
end
|
|
end
|
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|
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`state_read_gs_6: begin
|
|
digit_ready <= 0;
|
|
state <= `state_idle;
|
end
|
end
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|
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// 0 : Ignore if not in manual
|
// 0 : Ignore if not in manual
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// Clear gs_ram_addr
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// Clear gs_ram_addr
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// 1 : Synchronize with d10
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// 1 : Synchronize with d10
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