| Line 119... |
Line 119... |
`define state_read_gs_2 6'd31
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`define state_read_gs_2 6'd31
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`define state_read_gs_3 6'd32
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`define state_read_gs_3 6'd32
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`define state_read_gs_4 6'd33
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`define state_read_gs_4 6'd33
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`define state_read_gs_5 6'd34
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`define state_read_gs_5 6'd34
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`define state_read_gs_6 6'd35
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`define state_read_gs_6 6'd35
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`define state_write_gs_1 6'd36
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`define state_clear_drum_1 6'd50
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`define state_write_gs_2 6'd37
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`define state_clear_drum_2 6'd51
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`define state_write_gs_3 6'd38
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`define state_clear_drum_3 6'd52
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`define state_write_gs_4 6'd39
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`define state_write_gs_5 6'd40
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`define state_clear_drum_1 6'd41
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`define state_clear_drum_2 6'd42
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`define state_clear_drum_3 6'd43
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`define state_load_gs_1 6'd44
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`define state_load_gs_1 6'd45
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always @(posedge clk) begin
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always @(posedge clk) begin
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if (rst) begin
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if (rst) begin
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console_to_addr <= 0;
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console_to_addr <= 0;
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pgm_start <= 0;
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pgm_start <= 0;
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| Line 197... |
Line 203... |
end else if (do_reset_console) begin
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end else if (do_reset_console) begin
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do_reset_console <= 0;
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do_reset_console <= 0;
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state <= `state_reset_console_1;
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state <= `state_reset_console_1;
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end else if (do_clear_drum) begin
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end else if (do_clear_drum) begin
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do_clear_drum <= 0;
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do_clear_drum <= 0;
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gs_ram_addr <= 15'd0;
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state <= `state_clear_drum_1;
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state <= `state_clear_drum_1;
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end else if (do_pgm_reset) begin
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end else if (do_pgm_reset) begin
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do_pgm_reset <= 0;
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do_pgm_reset <= 0;
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state <= `state_pgm_reset_1;
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state <= `state_pgm_reset_1;
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end else if (do_acc_reset) begin
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end else if (do_acc_reset) begin
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| Line 427... |
Line 432... |
busy <= 1;
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busy <= 1;
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state <= `state_read_gs_1;
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state <= `state_read_gs_1;
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end
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end
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end
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end
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// Write word to general storage:
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// --> 4 digits address, little-endian
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// <-- dx digit, sign digit, d1-d10
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// 0: Ignore if not in manual
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// 1: Readin low-order addr digit
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// 2: Readin remaining addr digits
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// 3: Synchronize with d10
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// digit_ready <- 1
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// 4: Readin first digit
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// 5: Write digit
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// Readin next digit
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// 6: Cleanup
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`cmd_write_gs: begin
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`cmd_write_gs: begin
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if (ctl_sw_manual) begin
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busy <= 1;
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state <= `state_write_gs_1;
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end
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end
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end
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end
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`cmd_read_acc: begin
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`cmd_read_acc: begin
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end
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end
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`cmd_read_dist: begin
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`cmd_read_dist: begin
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end
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end
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| Line 457... |
Line 479... |
do_clear_drum <= 1;
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do_clear_drum <= 1;
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end
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end
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end
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end
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`cmd_load_gs: begin
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`cmd_load_gs: begin
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if (ctl_sw_manual) begin
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busy <= 1;
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state <= `state_load_gs_1;
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digit_ready <= 1;
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end
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end
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end
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`cmd_dump_gs: begin
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`cmd_dump_gs: begin
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end
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end
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`cmd_power_on_reset: begin
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`cmd_power_on_reset: begin
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busy <= 1;
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do_power_on_reset <= 1;
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end
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end
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`cmd_reset_console: begin
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`cmd_reset_console: begin
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busy <= 1;
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do_reset_console <= 1;
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end
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end
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`cmd_hard_reset: begin
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`cmd_hard_reset: begin
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busy <= 1;
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busy <= 1;
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do_hard_reset <= 1;
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do_hard_reset <= 1;
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| Line 688... |
Line 719... |
`state_read_gs_6: begin
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`state_read_gs_6: begin
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digit_ready <= 0;
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digit_ready <= 0;
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state <= `state_idle;
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state <= `state_idle;
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end
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end
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// Write word to general storage:
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// --> 4 digits address, little-endian
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// <-- dx digit, sign digit, d1-d10
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// 0: Ignore if not in manual
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// 1: Readin low-order addr digit
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// 2: Readin remaining addr digits
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// 3: Synchronize with d10
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// digit_ready <- 1
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// 4: Readin and write digit
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// 5: Write digit
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// Readin next digit
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// 6: Cleanup
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`state_write_gs_1: begin
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if (dx) begin
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state <= `state_write_gs_2;
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digit_ready <= 1;
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gs_addr_u <= cmd_digit_in;
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end
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end
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`state_write_gs_2: begin
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if (d0) gs_addr_t <= cmd_digit_in;
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else if (d1) gs_addr_h <= cmd_digit_in;
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else if (d2) begin
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gs_addr_th <= cmd_digit_in;
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state <= `state_write_gs_3;
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digit_ready <= 0;
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end
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end
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`state_write_gs_3: begin
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if (d10) begin
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gs_ram_addr <= gs_word_addr;
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digit_ready <= 1;
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state <= `state_write_gs_4;
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end
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end
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`state_write_gs_4: begin
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write_gs <= 1;
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console_out <= cmd_digit_in;
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gs_ram_addr <= gs_ram_addr + 1;
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if (d10) begin
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digit_ready <= 0;
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state <= `state_write_gs_5;
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end
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end
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`state_write_gs_5: begin
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write_gs <= 0;
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state <= `state_idle;
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end
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// 0 : Ignore if not in manual
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// 0 : Ignore if not in manual
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// Clear gs_ram_addr
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// Clear gs_ram_addr
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// 1 : Synchronize with d10
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// 1 : Synchronize with d10
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// Turn on console_write_gs
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// Turn on console_write_gs
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// 2 : Put a digit:
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// 2 : Put a digit:
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| Line 699... |
Line 784... |
// d0: minus
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// d0: minus
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// d1-d10: zero
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// d1-d10: zero
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// gs_ram_addr++
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// gs_ram_addr++
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`state_clear_drum_1: begin
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`state_clear_drum_1: begin
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if (d10) begin
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if (d10) begin
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console_out <= `biq_blank;
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gs_ram_addr <= 15'd0;
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write_gs <= 1;
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state <= `state_clear_drum_2;
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state <= `state_clear_drum_2;
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end
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end
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end
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end
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`state_clear_drum_2: begin
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`state_clear_drum_2: begin
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write_gs <= 1;
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console_out <= dx? `biq_blank
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console_out <= dx? `biq_blank
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: d0? `biq_minus
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: d0? `biq_minus
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: `biq_0;
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: `biq_0;
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if (write_gs)
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gs_ram_addr <= gs_ram_addr + 1;
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gs_ram_addr <= gs_ram_addr + 1;
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if (gs_ram_addr == 15'd23999) begin
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if (gs_ram_addr == 15'd23999) begin
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write_gs <= 0;
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write_gs <= 0;
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state <= `state_idle;
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state <= `state_idle;
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end
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end
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end
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end
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`state_load_gs_1: begin
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gs_ram_addr <= 15'd0;
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write_gs <= 1;
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console_out <= cmd_digit_in;
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state <= `state_load_gs_2;
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end
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`state_load_gs_2: begin
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gs_ram_addr <= gs_ram_addr + 1;
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console_out <= cmd_digit_in;
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if (gs_ram_addr == 15d'23999) begin
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write_gs <= 0;
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digit_ready <= 0;
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state <= `state_idle;
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end
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end
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endcase;
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endcase;
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end
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end
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end;
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end;
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always @(posedge ap) begin
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always @(posedge ap) begin
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