| Line 41... |
Line 41... |
prog_ontime,
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prog_ontime,
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input [0:5] command,
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input [0:5] command,
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output reg[0:6] data_out, addr_out, console_out,
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output reg[0:6] data_out, addr_out, console_out,
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output [0:6] display_digit,
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output [0:6] display_digit,
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output reg console_to_addr,
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output reg console_to_addr, acc_ri_console,
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output reg[0:14] gs_ram_addr,
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output reg[0:14] gs_ram_addr,
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output reg read_gs, write_gs,
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output reg read_gs, write_gs,
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output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
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output reg pgm_start, pgm_stop, err_reset, err_sense_reset,
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output run_control, half_or_pgm_stop, ri_storage, ro_storage,
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output run_control, half_or_pgm_stop, ri_storage, ro_storage,
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storage_control,
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storage_control,
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| Line 141... |
Line 141... |
`define state_read_dist_2 6'd45
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`define state_read_dist_2 6'd45
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`define state_read_dist_3 6'd46
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`define state_read_dist_3 6'd46
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`define state_read_prog_1 6'd47
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`define state_read_prog_1 6'd47
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`define state_read_prog_2 6'd48
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`define state_read_prog_2 6'd48
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`define state_read_prog_3 6'd49
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`define state_read_prog_3 6'd49
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`define state_clear_drum_1 6'd50
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`define state_write_acc_1 6'd50
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`define state_clear_drum_2 6'd51
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`define state_write_acc_2 6'd51
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`define state_clear_drum_3 6'd52
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`define state_write_acc_3 6'd52
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`define state_load_gs_1 6'd53
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`define state_clear_drum_1 6'd53
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`define state_load_gs_2 6'd54
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`define state_clear_drum_2 6'd54
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`define state_dump_gs_1 6'd55
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`define state_clear_drum_3 6'd55
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`define state_dump_gs_2 6'd56
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`define state_load_gs_1 6'd56
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`define state_dump_gs_3 6'd57
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`define state_load_gs_2 6'd57
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`define state_dump_gs_4 6'd58
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`define state_dump_gs_1 6'd58
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`define state_dump_gs_2 6'd59
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`define state_dump_gs_3 6'd60
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`define state_dump_gs_4 6'd61
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always @(posedge clk)
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always @(posedge clk)
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if (rst) begin
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if (rst) begin
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console_to_addr <= 0;
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console_to_addr <= 0;
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pgm_start <= 0;
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pgm_start <= 0;
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| Line 198... |
Line 201... |
do_clear_drum <= 0;
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do_clear_drum <= 0;
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gs_ram_addr <= 15'd0;
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gs_ram_addr <= 15'd0;
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read_gs <= 0;
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read_gs <= 0;
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write_gs <= 0;
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write_gs <= 0;
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acc_ri_console <= 0;
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console_out <= `biq_blank;
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console_out <= `biq_blank;
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end else if (dp) begin
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end else if (dp) begin
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case (state)
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case (state)
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`state_idle: begin
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`state_idle: begin
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case (command)
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case (command)
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| Line 220... |
Line 224... |
hard_reset <= 1;
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hard_reset <= 1;
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state <= `state_hard_reset_1;
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state <= `state_hard_reset_1;
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end else if (do_reset_console) begin
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end else if (do_reset_console) begin
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do_reset_console <= 0;
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do_reset_console <= 0;
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state <= `state_reset_console_1;
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state <= `state_reset_console_1;
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end else if (do_clear_drum) begin
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do_clear_drum <= 0;
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state <= `state_clear_drum_1;
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end else if (do_pgm_reset) begin
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end else if (do_pgm_reset) begin
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do_pgm_reset <= 0;
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do_pgm_reset <= 0;
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state <= `state_pgm_reset_1;
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state <= `state_pgm_reset_1;
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end else if (do_acc_reset) begin
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end else if (do_acc_reset) begin
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do_acc_reset <= 0;
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do_acc_reset <= 0;
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| Line 238... |
Line 239... |
state <= `state_err_reset_1;
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state <= `state_err_reset_1;
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end else if (do_err_sense_reset) begin
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end else if (do_err_sense_reset) begin
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do_err_sense_reset <= 0;
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do_err_sense_reset <= 0;
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err_sense_reset <= 1;
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err_sense_reset <= 1;
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state <= `state_err_sense_reset_1;
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state <= `state_err_sense_reset_1;
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end else if (do_clear_drum) begin
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do_clear_drum <= 0;
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state <= `state_clear_drum_1;
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end else begin
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end else begin
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busy <= 0;
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busy <= 0;
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digit_ready <= 0;
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digit_ready <= 0;
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end
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end
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end
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end
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| Line 485... |
Line 489... |
`cmd_read_prog: begin
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`cmd_read_prog: begin
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busy <= 1;
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busy <= 1;
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state <= `state_read_prog_1;
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state <= `state_read_prog_1;
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end
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end
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`cmd_write_acc: begin
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busy <= 1;
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state <= `state_write_acc_1;
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end
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// 0 : Ignore if not in manual
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// 0 : Ignore if not in manual
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// Clear gs_ram_addr
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// Clear gs_ram_addr
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// 1 : Synchronize with d10
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// 1 : Synchronize with d10
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// Turn on console_write_gs
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// Turn on console_write_gs
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// 2 : Put a digit:
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// 2 : Put a digit:
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| Line 858... |
Line 867... |
`state_read_prog_3: begin
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`state_read_prog_3: begin
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digit_ready <= 0;
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digit_ready <= 0;
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state <= `state_idle;
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state <= `state_idle;
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end
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end
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`state_write_acc_1: begin
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if (wu & d10) begin
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console_out <= cmd_digit_in;
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acc_ri_console <= 1;
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digit_ready <= 1;
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state <= `state_write_acc_2;
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end
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end
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`state_write_acc_2: begin
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console_out <= cmd_digit_in;
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if (wu & d10) begin
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digit_ready <= 0;
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state <= `state_write_acc_3;
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end
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end
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`state_write_acc_3: begin
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acc_ri_console <= 0;
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state <= `state_idle;
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end
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// 0 : Ignore if not in manual
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// 0 : Ignore if not in manual
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// 1 : Synchronize with dx
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// 1 : Synchronize with dx
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// Put first dx digit
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// Put first dx digit
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// 2 : Put a digit:
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// 2 : Put a digit:
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// dx: blank
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// dx: blank
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