| Line 38... |
Line 38... |
input [0:3] early_idx, ontime_idx,
|
input [0:3] early_idx, ontime_idx,
|
|
|
input [0:6] cmd_digit_in, io_buffer_in, gs_in, acc_ontime, dist_ontime,
|
input [0:6] cmd_digit_in, io_buffer_in, gs_in, acc_ontime, dist_ontime,
|
prog_ontime,
|
prog_ontime,
|
input [0:5] command,
|
input [0:5] command,
|
|
input restart_reset,
|
|
|
output reg[0:6] data_out, addr_out, console_out,
|
output reg[0:6] data_out, addr_out, console_out,
|
output [0:6] display_digit,
|
output [0:6] display_digit,
|
output reg console_to_addr, acc_ri_console,
|
output reg console_to_addr, acc_ri_console,
|
output reg[0:14] gs_ram_addr,
|
output reg[0:14] gs_ram_addr,
|
| Line 51... |
Line 52... |
storage_control,
|
storage_control,
|
output reg man_pgm_reset, man_acc_reset, hard_reset,
|
output reg man_pgm_reset, man_acc_reset, hard_reset,
|
output set_8000, reset_8000,
|
output set_8000, reset_8000,
|
|
|
output reg[0:6] cmd_digit_out,
|
output reg[0:6] cmd_digit_out,
|
output reg busy, digit_ready,
|
output reg busy, digit_ready, restart_reset_busy,
|
output reg punch_card, read_card, card_digit_ready
|
output reg punch_card, read_card, card_digit_ready
|
);
|
);
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Operator console switch settings and their control signals.
|
// Operator console switch settings and their control signals.
|
| Line 188... |
Line 189... |
|
|
state <= `state_idle;
|
state <= `state_idle;
|
busy <= 1;
|
busy <= 1;
|
digit_ready <= 0;
|
digit_ready <= 0;
|
cmd_digit_out <= `biq_blank;
|
cmd_digit_out <= `biq_blank;
|
|
restart_reset_busy <= 0;
|
|
|
do_power_on_reset <= 1;
|
do_power_on_reset <= 1;
|
do_reset_console <= 0;
|
do_reset_console <= 0;
|
do_err_reset <= 0;
|
do_err_reset <= 0;
|
do_err_sense_reset <= 0;
|
do_err_sense_reset <= 0;
|
| Line 208... |
Line 210... |
end else if (dp) begin
|
end else if (dp) begin
|
case (state)
|
case (state)
|
`state_idle: begin
|
`state_idle: begin
|
case (command)
|
case (command)
|
`cmd_none: begin
|
`cmd_none: begin
|
if (do_power_on_reset) begin
|
if (restart_reset) begin
|
|
do_pgm_reset <= 1;
|
|
do_acc_reset <= 1;
|
|
do_err_reset <= 1;
|
|
restart_reset_busy <= 1;
|
|
end else if (do_power_on_reset) begin
|
do_power_on_reset <= 0;
|
do_power_on_reset <= 0;
|
do_reset_console <= 1;
|
do_reset_console <= 1;
|
do_pgm_reset <= 1;
|
do_pgm_reset <= 1;
|
do_acc_reset <= 1;
|
do_acc_reset <= 1;
|
do_err_reset <= 1;
|
do_err_reset <= 1;
|
| Line 245... |
Line 252... |
do_clear_drum <= 0;
|
do_clear_drum <= 0;
|
state <= `state_clear_drum_1;
|
state <= `state_clear_drum_1;
|
end else begin
|
end else begin
|
busy <= 0;
|
busy <= 0;
|
digit_ready <= 0;
|
digit_ready <= 0;
|
|
restart_reset_busy <= 0;
|
end
|
end
|
end
|
end
|
|
|
`cmd_pgm_sw_stop: begin
|
`cmd_pgm_sw_stop: begin
|
busy <= 1;
|
busy <= 1;
|
| Line 868... |
Line 876... |
digit_ready <= 0;
|
digit_ready <= 0;
|
state <= `state_idle;
|
state <= `state_idle;
|
end
|
end
|
|
|
`state_write_acc_1: begin
|
`state_write_acc_1: begin
|
if (wu & d10) begin
|
if (wl & dx) begin
|
console_out <= cmd_digit_in;
|
console_out <= cmd_digit_in;
|
acc_ri_console <= 1;
|
acc_ri_console <= 1;
|
digit_ready <= 1;
|
digit_ready <= 1;
|
state <= `state_write_acc_2;
|
state <= `state_write_acc_2;
|
end
|
end
|
