| Line 165... |
Line 165... |
wire dc_all_restarts, dc_use_d_for_i, dc_turn_on_single_intlk,
|
wire dc_all_restarts, dc_use_d_for_i, dc_turn_on_single_intlk,
|
dc_turn_on_op_intlk, dc_stop_code, dc_code_69, dc_tlu_sig, dc_mult_sig,
|
dc_turn_on_op_intlk, dc_stop_code, dc_code_69, dc_tlu_sig, dc_mult_sig,
|
dc_divide_sig, dc_reset_sig, dc_no_reset_sig, dc_abs_sig, dc_no_abs_sig,
|
dc_divide_sig, dc_reset_sig, dc_no_reset_sig, dc_abs_sig, dc_no_abs_sig,
|
dc_lower_sig, dc_upper_sig, dc_add_sig, dc_subt_sig, dc_right_shift_sig,
|
dc_lower_sig, dc_upper_sig, dc_add_sig, dc_subt_sig, dc_right_shift_sig,
|
dc_left_shift_sig, dc_half_correct_sig, dc_shift_count_sig,
|
dc_left_shift_sig, dc_half_correct_sig, dc_shift_count_sig,
|
dc_overflow_sense_latch;
|
dc_end_shift_control, dc_overflow_sense_latch;
|
|
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
// Distributor
|
// Distributor
|
//-----------------------------------------------------------------------------
|
//-----------------------------------------------------------------------------
|
wire [0:6] ds_early_out, ds_ontime_out;
|
wire [0:6] ds_early_out, ds_ontime_out;
|
| Line 245... |
Line 245... |
.acc_early_out(ac_early_out),
|
.acc_early_out(ac_early_out),
|
.acc_ontime_out(ac_ontime_out),
|
.acc_ontime_out(ac_ontime_out),
|
.prog_step_early_out(ps_early_out),
|
.prog_step_early_out(ps_early_out),
|
.select_storage_out(ss_selected_out),
|
.select_storage_out(ss_selected_out),
|
.addr_u(ar_addr_u),
|
.addr_u(ar_addr_u),
|
.acc_true_add_gate(1'b0), //
|
.acc_true_add_gate(1'b0), // 85o
|
.acc_compl_add_gate(1'b0), //
|
.acc_compl_add_gate(1'b0), // 85r
|
.left_shift_gate(1'b0), //
|
.left_shift_gate(1'b0), // 85b
|
.prog_step_add_gate(1'b0), //
|
.prog_step_add_gate(tl_prog_add),
|
.shift_num_gate(1'b0), //
|
.shift_num_gate(1'b0), // 85a
|
.select_stor_add_gate(tl_sel_stor_add_gate),
|
.select_stor_add_gate(tl_sel_stor_add_gate),
|
.adder_entry_a(aa_entry_a)
|
.adder_entry_a(aa_entry_a)
|
);
|
);
|
|
|
add_in_b ab (
|
add_in_b ab (
|
.dist_early_out(ds_early_out),
|
.dist_early_out(ds_early_out),
|
.dist_ontime_out(ds_ontime_out),
|
.dist_ontime_out(ds_ontime_out),
|
.special_int_entry(tl_special_digit),
|
.special_int_entry(tl_special_digit),
|
.ontime_dist_add_gate_tlu(tl_ontime_dist_add_gate),
|
.ontime_dist_add_gate_tlu(tl_ontime_dist_add_gate),
|
.dist_compl_add_gate(1'b0), //
|
.dist_compl_add_gate(1'b0), // 85r
|
.upper_lower_check(tl_upper_lower_check),
|
.upper_lower_check(tl_upper_lower_check),
|
.dist_blank_gate(tl_dist_blank_gate),
|
.dist_blank_gate(tl_dist_blank_gate),
|
.early_dist_zero_entry(1'b0), //
|
.early_dist_zero_entry(tl_early_dist_zero_entry),
|
.dist_true_add_gate(1'b0), //
|
.dist_true_add_gate(1'b0), // 85r
|
.adder_entry_b(ab_entry_b)
|
.adder_entry_b(ab_entry_b)
|
);
|
);
|
|
|
accumulator ac (
|
accumulator ac (
|
.rst(oc_hard_reset),
|
.rst(oc_hard_reset),
|
| Line 282... |
Line 282... |
.d0u(d0u),
|
.d0u(d0u),
|
.wu(wu),
|
.wu(wu),
|
.wl(wl),
|
.wl(wl),
|
.adder_out(ad_adder_out),
|
.adder_out(ad_adder_out),
|
.console_out(oc_console_out),
|
.console_out(oc_console_out),
|
.acc_regen_gate(1'b1), //
|
.acc_regen_gate(1'b1), // 85c
|
.right_shift_gate(1'b0), //
|
.right_shift_gate(1'b0), // 85f
|
.acc_ri_gate(1'b0), //
|
.acc_ri_gate(1'b0), // 85c
|
.acc_ri_console(oc_acc_ri_console),
|
.acc_ri_console(oc_acc_ri_console),
|
.zero_shift_count(1'b0), //
|
.zero_shift_count(1'b0), // 85b
|
.man_acc_reset(oc_man_acc_reset),
|
.man_acc_reset(oc_man_acc_reset),
|
.reset_op(dc_reset_sig),
|
.reset_op(dc_reset_sig),
|
.early_idx(early_idx),
|
.early_idx(early_idx),
|
.ontime_idx(ontime_idx),
|
.ontime_idx(ontime_idx),
|
.early_out(ac_early_out),
|
.early_out(ac_early_out),
|
| Line 311... |
Line 311... |
.d10(d10),
|
.d10(d10),
|
.d10u(d10u),
|
.d10u(d10u),
|
.wl(wl),
|
.wl(wl),
|
.entry_a(aa_entry_a),
|
.entry_a(aa_entry_a),
|
.entry_b(ab_entry_b),
|
.entry_b(ab_entry_b),
|
.tlu_on(1'b0), //
|
.tlu_on(tl_tlu_on),
|
.left_shift_off(1'b1), //
|
.left_shift_off(1'b1), // 85d
|
.left_shift_on(1'b0), //
|
.left_shift_on(1'b0), // 85d
|
.no_carry_insert(1'b0), //
|
.no_carry_insert(1'b0), // 85e
|
.no_carry_blank(1'b0), //
|
.no_carry_blank(1'b0), // 85e
|
.carry_insert(1'b0), //
|
.carry_insert(1'b0), // 85e
|
.carry_blank(1'b0), //
|
.carry_blank(1'b0), // 85e
|
.zero_insert(1'b0), //
|
.zero_insert(1'b0), // 85j
|
.error_reset(oc_err_reset),
|
.error_reset(oc_err_reset),
|
.quotient_digit_on(1'b0), //
|
.quotient_digit_on(1'b0), // 85p
|
.overflow_stop_sw(oc_ovflw_stop_sw),
|
.overflow_stop_sw(oc_ovflw_stop_sw),
|
.overflow_sense_sw(oc_ovflw_sense_sw),
|
.overflow_sense_sw(oc_ovflw_sense_sw),
|
.mult_div_off(1'b0), //
|
.mult_div_off(1'b0), // 85k
|
.dist_true_add_gate(1'b0), //
|
.dist_true_add_gate(1'b0), // 85r
|
.acc_true_add_latch(1'b0), //
|
.acc_true_add_latch(1'b0), // 85r
|
.shift_overflow(1'b0), //
|
.shift_overflow(1'b0), // 85b
|
.adder_out(ad_adder_out),
|
.adder_out(ad_adder_out),
|
.carry_test(ad_carry_test),
|
.carry_test(ad_carry_test),
|
.no_carry_test(ad_no_carry_test),
|
.no_carry_test(ad_no_carry_test),
|
.d0l_carry_sig(ad_d0l_carry_sig),
|
.d0l_carry_sig(ad_d0l_carry_sig),
|
.overflow_stop(ad_overflow_stop),
|
.overflow_stop(ad_overflow_stop),
|
| Line 372... |
Line 372... |
.set_8000(oc_set_8000),
|
.set_8000(oc_set_8000),
|
.reset_8000(oc_reset_8000),
|
.reset_8000(oc_reset_8000),
|
.tlu_band_change(tl_tlu_band_change),
|
.tlu_band_change(tl_tlu_band_change),
|
.double_write(gs_double_write),
|
.double_write(gs_double_write),
|
.no_write(gs_no_write),
|
.no_write(gs_no_write),
|
.bs_to_gs(1'b0), //
|
.bs_to_gs(1'b0), // 87b ***
|
.rigs(cc_rigs),
|
.rigs(cc_rigs),
|
.ps_reg_in(ps_ontime_out),
|
.ps_reg_in(ps_ontime_out),
|
.console_in(oc_addr_out),
|
.console_in(oc_addr_out),
|
.ri_addr_reg(op_ri_addr_reg),
|
.ri_addr_reg(op_ri_addr_reg),
|
.console_to_addr_reg(oc_console_to_addr),
|
.console_to_addr_reg(oc_console_to_addr),
|
| Line 436... |
Line 436... |
.manual_error_reset_sw(oc_err_reset),
|
.manual_error_reset_sw(oc_err_reset),
|
.half_or_pgm_stop(oc_half_or_pgm_stop),
|
.half_or_pgm_stop(oc_half_or_pgm_stop),
|
.prog_restart(ps_restart_sig),
|
.prog_restart(ps_restart_sig),
|
.error_stop(es_err_stop),
|
.error_stop(es_err_stop),
|
.error_sense_restart(es_err_sense_restart),
|
.error_sense_restart(es_err_sense_restart),
|
.arith_restart(1'b0), //
|
.arith_restart(1'b0), // 85d
|
.stop_code(dc_stop_code),
|
.stop_code(dc_stop_code),
|
.code_69(dc_code_69),
|
.code_69(dc_code_69),
|
.start_10s_60s(dc_turn_on_single_intlk),
|
.start_10s_60s(dc_turn_on_single_intlk),
|
.end_shift_cntrl(1'b0), //
|
.end_shift_cntrl(dc_end_shift_control),
|
.tlu_on(tl_tlu_on),
|
.tlu_on(tl_tlu_on),
|
.end_of_operation(1'b0), //
|
.end_of_operation(1'b0), // 85d
|
.turn_on_op_intlk(dc_turn_on_op_intlk),
|
.turn_on_op_intlk(dc_turn_on_op_intlk),
|
.decode_restarts(dc_all_restarts),
|
.decode_restarts(dc_all_restarts),
|
.use_d_for_i(dc_use_d_for_i),
|
.use_d_for_i(dc_use_d_for_i),
|
.dist_back_signal(ds_back_sig),
|
.dist_back_signal(ds_back_sig),
|
.error_stop_ed0u(es_err_stop_ed0u),
|
.error_stop_ed0u(es_err_stop_ed0u),
|
.divide_overflow_stop(1'b0), //
|
.divide_overflow_stop(1'b0), // 68a ***
|
.exceed_address_or_stor_select_light(1'b0), //
|
.exceed_address_or_stor_select_light(1'b0), // 71a ***
|
.opreg_t(op_opreg_t),
|
.opreg_t(op_opreg_t),
|
.opreg_u(op_opreg_u),
|
.opreg_u(op_opreg_u),
|
.addr_no_800x(ar_addr_no_800x),
|
.addr_no_800x(ar_addr_no_800x),
|
.addr_8001(ar_addr_8001),
|
.addr_8001(ar_addr_8001),
|
.dynamic_addr_hit(ar_dynamic_addr_hit),
|
.dynamic_addr_hit(ar_dynamic_addr_hit),
|
| Line 527... |
Line 527... |
.addr_u(ar_addr_u),
|
.addr_u(ar_addr_u),
|
.ontime_dist(ds_ontime_out),
|
.ontime_dist(ds_ontime_out),
|
.man_ro_storage(cc_man_ro_storage),
|
.man_ro_storage(cc_man_ro_storage),
|
.dist_back_sig(ds_back_sig),
|
.dist_back_sig(ds_back_sig),
|
.d_control(cc_d_control),
|
.d_control(cc_d_control),
|
.ena_arith_codes(1'b0), //
|
.ena_arith_codes(1'b0), // 81i ***
|
.pgm_stop_sw(oc_pgm_stop_sw),
|
.pgm_stop_sw(oc_pgm_stop_sw),
|
.acc_zero_test(zc_acc_zero_test),
|
.acc_zero_test(zc_acc_zero_test),
|
.acc_no_zero_test(zc_acc_no_zero_test),
|
.acc_no_zero_test(zc_acc_no_zero_test),
|
.acc_plus_test(1'b0), //
|
.acc_plus_test(1'b0), // 85t
|
.acc_minus_test(1'b0), //
|
.acc_minus_test(1'b0), // 85t
|
.single_intlk(cc_single_intlk),
|
.single_intlk(cc_single_intlk),
|
.arith_restart(1'b0), //
|
.arith_restart(1'b0), // 85d
|
.overflow_sense_sig(ad_overflow_sense_sig),
|
.overflow_sense_sig(ad_overflow_sense_sig),
|
.man_acc_reset(oc_man_acc_reset),
|
.man_acc_reset(oc_man_acc_reset),
|
.all_restarts(dc_all_restarts),
|
.all_restarts(dc_all_restarts),
|
.use_d_for_i(dc_use_d_for_i),
|
.use_d_for_i(dc_use_d_for_i),
|
.turn_on_single_intlk(dc_turn_on_single_intlk),
|
.turn_on_single_intlk(dc_turn_on_single_intlk),
|
| Line 558... |
Line 558... |
.subt_sig(dc_subt_sig),
|
.subt_sig(dc_subt_sig),
|
.right_shift_sig(dc_right_shift_sig),
|
.right_shift_sig(dc_right_shift_sig),
|
.left_shift_sig(dc_left_shift_sig),
|
.left_shift_sig(dc_left_shift_sig),
|
.half_correct_sig(dc_half_correct_sig),
|
.half_correct_sig(dc_half_correct_sig),
|
.shift_count_sig(dc_shift_count_sig),
|
.shift_count_sig(dc_shift_count_sig),
|
|
.end_shift_control(dc_end_shift_control),
|
.overflow_sense_latch(dc_overflow_sense_latch)
|
.overflow_sense_latch(dc_overflow_sense_latch)
|
);
|
);
|
|
|
distributor ds (
|
distributor ds (
|
.rst(oc_hard_reset),
|
.rst(oc_hard_reset),
|
| Line 593... |
Line 594... |
.d10(d10),
|
.d10(d10),
|
.wl(wl),
|
.wl(wl),
|
.err_restart_sw(oc_err_restart_sw),
|
.err_restart_sw(oc_err_restart_sw),
|
.err_reset(oc_err_reset),
|
.err_reset(oc_err_reset),
|
.err_sense_reset(oc_err_sense_reset),
|
.err_sense_reset(oc_err_sense_reset),
|
.clock_err_sig(1'b0), //
|
.clock_err_sig(1'b0), // not possible
|
.err_stop_sig(ck_error_stop),
|
.err_stop_sig(ck_error_stop),
|
.restart_reset_busy(oc_restart_reset_busy),
|
.restart_reset_busy(oc_restart_reset_busy),
|
.err_stop(es_err_stop),
|
.err_stop(es_err_stop),
|
.err_sense_light(es_err_sense_light),
|
.err_sense_light(es_err_sense_light),
|
.err_stop_ed0u(es_err_stop_ed0u),
|
.err_stop_ed0u(es_err_stop_ed0u),
|
| Line 738... |
Line 739... |
.addr_hot_8000(1'b0), // *** see cc
|
.addr_hot_8000(1'b0), // *** see cc
|
.acc_ontime(ac_ontime_out),
|
.acc_ontime(ac_ontime_out),
|
.dist_ontime(ds_ontime_out),
|
.dist_ontime(ds_ontime_out),
|
.gs_out(tr_gs_out),
|
.gs_out(tr_gs_out),
|
.console_switches(oc_data_out),
|
.console_switches(oc_data_out),
|
.acc_plus(1'b0), //
|
.acc_plus(1'b0), // 85o
|
.acc_minus(1'b0), //
|
.acc_minus(1'b0), // 85o
|
.selected_out(ss_selected_out)
|
.selected_out(ss_selected_out)
|
);
|
);
|
|
|
tlu tl (
|
tlu tl (
|
.rst(oc_hard_reset),
|
.rst(oc_hard_reset),
|
| Line 775... |
Line 776... |
.s3(s3),
|
.s3(s3),
|
.s4(s4),
|
.s4(s4),
|
.tlu_sig(dc_tlu_sig),
|
.tlu_sig(dc_tlu_sig),
|
.upper_sig(dc_upper_sig),
|
.upper_sig(dc_upper_sig),
|
.lower_sig(dc_lower_sig),
|
.lower_sig(dc_lower_sig),
|
.divide_on(1'b0), //
|
.divide_on(1'b0), // 85p
|
.mult_nozero_edxl(1'b0), //
|
.mult_nozero_edxl(1'b0), // 85j
|
.carry_test_latch(ad_carry_test),
|
.carry_test_latch(ad_carry_test),
|
.tlu_or_acc_zero_check(ca_check_latch),
|
.tlu_or_acc_zero_check(ca_check_latch),
|
.man_acc_reset(oc_man_acc_reset),
|
.man_acc_reset(oc_man_acc_reset),
|
.reset_sig(dc_reset_sig),
|
.reset_sig(dc_reset_sig),
|
.no_reset_sig(dc_no_reset_sig),
|
.no_reset_sig(dc_no_reset_sig),
|
.acc_minus_sign(1'b0), //
|
.acc_minus_sign(1'b0), // 85t
|
.compl_adj(1'b0), //
|
.compl_adj(1'b0), // 85s
|
.quot_digit_on(1'b0), //
|
.quot_digit_on(1'b0), // 85p
|
.dist_compl_add(1'b0), //
|
.dist_compl_add(1'b0), // 85p
|
.any_left_shift_on(1'b0), //
|
.any_left_shift_on(1'b0), // 85j
|
.right_shift_on(1'b0), //
|
.right_shift_on(1'b0), // 85a
|
.left_shift_on(1'b0), //
|
.left_shift_on(1'b0), // 85b
|
.mult_div_left_shift(1'b0), //
|
.mult_div_left_shift(1'b0), // 85k
|
.sig_digit_on(1'b0), //
|
.sig_digit_on(1'b0), // 85j
|
.hc_add_5(1'b0), //
|
.hc_add_5(1'b0), // 85a
|
.mult_on(1'b0), //
|
.mult_on(1'b0), // 85q
|
.acc_true_add_gate(1'b0), //
|
.acc_true_add_gate(1'b0), // 85d
|
.tlu_on(tl_tlu_on),
|
.tlu_on(tl_tlu_on),
|
.early_dist_zero_entry(tl_early_dist_zero_entry),
|
.early_dist_zero_entry(tl_early_dist_zero_entry),
|
.early_dist_zero_control(tl_early_dist_zero_control),
|
.early_dist_zero_control(tl_early_dist_zero_control),
|
.prog_to_acc_add(tl_prog_to_acc_add),
|
.prog_to_acc_add(tl_prog_to_acc_add),
|
.prog_add(tl_prog_add),
|
.prog_add(tl_prog_add),
|
| Line 814... |
Line 815... |
translators tr (
|
translators tr (
|
.dist_early_out(`biq_blank),
|
.dist_early_out(`biq_blank),
|
.bs_out(`biq_blank),
|
.bs_out(`biq_blank),
|
.console_out(oc_console_out),
|
.console_out(oc_console_out),
|
.ri_gs(cc_rigs),
|
.ri_gs(cc_rigs),
|
.ri_bs(1'b0), //
|
.ri_bs(1'b0), // 87b ***
|
.ri_console(oc_write_gs),
|
.ri_console(oc_write_gs),
|
.n800x(ar_addr_no_800x),
|
.n800x(ar_addr_no_800x),
|
.console_read_gs(oc_read_gs),
|
.console_read_gs(oc_read_gs),
|
.gs_out(gs_out),
|
.gs_out(gs_out),
|
.gs_write(tr_gs_write),
|
.gs_write(tr_gs_write),
|
