URL https://opencores.org/ocsvn/iicmb/iicmb/trunk

Subversion Repositories iicmb

[/] [iicmb/] [trunk/] [src/] [iicmb_m_av.vhd] - Diff between revs 2 and 3

Rev 2	Rev 3
Line 71...	Line 71...
`------------------------------------`	`------------------------------------`
`-- Avalon-MM signals:`	`-- Avalon-MM signals:`
`clk : in std_logic; -- Clock`	`clk : in std_logic; -- Clock`
`s_rst : in std_logic; -- Synchronous reset (active high)`	`s_rst : in std_logic; -- Synchronous reset (active high)`
`-------------`	`-------------`
`waitrequest : out std_logic;`	`waitrequest : out std_logic; -- Wait request`
`readdata : out std_logic_vector(31 downto 0);`	`readdata : out std_logic_vector(31 downto 0); -- Data from slave to master`
`readdatavalid : out std_logic;`	`readdatavalid : out std_logic; -- Data validity indication`
`writedata : in std_logic_vector(31 downto 0);`	`writedata : in std_logic_vector(31 downto 0); -- Data from master to slave`
`write : in std_logic;`	`write : in std_logic; -- Asserted to indicate write transfer`
`read : in std_logic;`	`read : in std_logic; -- Asserted to indicate read transfer`
`byteenable : in std_logic_vector( 3 downto 0);`	`byteenable : in std_logic_vector( 3 downto 0); -- Enables specific byte lane(s)`
`------------------------------------`	`------------------------------------`
`------------------------------------`	`------------------------------------`
`-- Interrupt request:`	`-- Interrupt request:`
`irq : out std_logic; -- Interrupt request`	`irq : out std_logic; -- Interrupt request`
`------------------------------------`	`------------------------------------`