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----------------------------------------------------------------------------------
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-- Company: VISENGI S.L. (www.visengi.com)
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-- Engineer: Victor Lopez Lorenzo (victor.lopez (at) visengi (dot) com)
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--
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-- Create Date: 19:34:36 04/November/2008
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-- Project Name: IMA ADPCM Encoder
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-- Tool versions: Xilinx ISE 9.2i
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-- Description:
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--
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-- Description: This project features a full-hardware sound compressor using the well known algorithm IMA ADPCM.
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-- The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player
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-- with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes
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-- an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file.
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-- Compression ratio is fixed for IMA-ADPCM, being 4:1.
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--
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--
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-- LICENSE TERMS: GNU GENERAL PUBLIC LICENSE Version 3
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--
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-- That is you may use it only in NON-COMMERCIAL projects.
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-- You are only required to include in the copyrights/about section
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-- that your system contains a "IMA ADPCM Encoder (C) VISENGI S.L. under GPL license"
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-- This holds also in the case where you modify the core, as the resulting core
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-- would be a derived work.
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-- Also, we would like to know if you use this core in a project of yours, just an email will do.
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--
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-- Please take good note of the disclaimer section of the GPL license, as we don't
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-- take any responsability for anything that this core does.
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity IMA_ADPCM_Encode is
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Port ( clk : in STD_LOGIC;
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reset : in STD_LOGIC;
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PredictedValue_o : out std_logic_vector(15 downto 0);
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StepIndex_o : out std_logic_vector(6 downto 0);
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StateRDY : out std_logic;
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sample : in std_logic_vector(15 downto 0); --don't change it while sample_rdy='1'
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sample_rdy : in std_logic; --lower it only when ADPCM_sample_rdy = '1'
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ADPCM_sample : out std_logic_vector(3 downto 0);
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ADPCM_sample_rdy : out std_logic
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);
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end IMA_ADPCM_Encode;
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architecture Behavioral of IMA_ADPCM_Encode is
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signal PredictedValue : std_logic_vector(15 downto 0);
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signal StepIndex : std_logic_vector(6 downto 0);
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component IMA_adpcm_steptable_rom port(
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addr0 : in STD_LOGIC_VECTOR(6 downto 0);
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clk : in STD_LOGIC;
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datao0: out STD_LOGIC_VECTOR(14 downto 0));
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end component;
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signal Step : std_logic_vector(14 downto 0);
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signal comp16b_AbtB : std_logic; --A bigger than B
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signal delta, diff : std_logic_vector(15 downto 0);
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signal State : integer range 0 to 31;
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begin
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StepTable_ROM : IMA_adpcm_steptable_rom port map (
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addr0 => StepIndex,
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clk => clk,
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datao0=> Step);
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process (reset, clk)
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variable AdderSub16 : std_logic_vector(15 downto 0);
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variable ADPCM_sample2 : std_logic_vector(3 downto 0);
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begin
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if (reset = '1') then
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State <= 0;
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AdderSub16 := (others => '0');
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ADPCM_sample <= x"0";
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ADPCM_sample2 := x"0";
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ADPCM_sample_rdy <= '0';
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PredictedValue <= (others => '0');
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StepIndex <= (others => '0');
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PredictedValue_o <= (others => '0');
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StepIndex_o <= (others => '0');
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StateRDY <= '0';
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delta <= (others => '0');
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diff <= (others => '0');
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comp16b_AbtB <= '0';
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elsif (clk='1' and clk'event) then
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ADPCM_sample_rdy <= '0';
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case State is
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when 0 =>
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PredictedValue_o <= PredictedValue; StepIndex_o <= StepIndex; StateRDY <= '1';
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if (sample_rdy = '1') then State <= 10; StateRDY <= '0'; end if;
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when 10 => --Signed comparison between A:sample and B:PredictedValue
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if (sample(15) = '1' and PredictedValue(15) = '0') then
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comp16b_AbtB <= '0'; --sample<0, Pred>=0
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elsif (sample(15) = '0' and PredictedValue(15) = '1') then
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comp16b_AbtB <= '1'; --sample>=0, Pred<0
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else --both positives or both negatives --> normal comparison
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if (sample > PredictedValue) then comp16b_AbtB <= '1'; else comp16b_AbtB <= '0'; end if;
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end if;
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State <= State + 1;
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when 11 =>
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if (comp16b_AbtB = '1') then --it really should be beq but a negative zero is as good as a positive one
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delta <= sample - PredictedValue;
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ADPCM_sample2(3) := '0';
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else
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delta <= PredictedValue - sample;
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ADPCM_sample2(3) := '1'; --set the sign (negative)
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end if;
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State <= State + 1;
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when 12 => --we've got the rigth Step now
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diff <= "0000" & Step(14 downto 3);
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if (delta > '0' & Step) then comp16b_AbtB <= '1'; else comp16b_AbtB <= '0'; end if;
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State <= State + 1;
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when 13 =>
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if (comp16b_AbtB = '1') then --delta > step
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delta <= delta - ('0' & Step);
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diff <= diff + ('0' & Step);
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ADPCM_sample2(2) := '1';
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else
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ADPCM_sample2(2) := '0';
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end if;
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State <= State + 1;
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when 14 =>
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if (delta > "00" & Step(14 downto 1)) then comp16b_AbtB <= '1'; else comp16b_AbtB <= '0'; end if;
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State <= State + 1;
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when 15 =>
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if (comp16b_AbtB = '1') then --delta > step
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delta <= delta - ("00" & Step(14 downto 1));
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diff <= diff + ("00" & Step(14 downto 1));
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ADPCM_sample2(1) := '1';
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else
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ADPCM_sample2(1) := '0';
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end if;
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State <= State + 1;
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when 16 =>
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if (delta > "000" & Step(14 downto 2)) then comp16b_AbtB <= '1'; else comp16b_AbtB <= '0'; end if;
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State <= State + 1;
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when 17 =>
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if (comp16b_AbtB = '1') then --delta > step
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diff <= diff + ("000" & Step(14 downto 2));
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ADPCM_sample2(0) := '1';
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else
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ADPCM_sample2(0) := '0';
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end if;
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ADPCM_sample_rdy <= '1';
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State <= State + 1;
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when 18 =>
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if (ADPCM_sample2(3) = '1') then --negative
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AdderSub16 := PredictedValue - diff;
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else
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AdderSub16 := PredictedValue + diff;
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end if;
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--IMA_ADPCMIndexTable[8] = -1, -1, -1, -1, 2, 4, 6, 8,
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case ADPCM_sample2(2 downto 0) is
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when "111" => StepIndex <= StepIndex + "0001000";
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when "110" => StepIndex <= StepIndex + "0000110";
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when "101" => StepIndex <= StepIndex + "0000100";
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when "100" => StepIndex <= StepIndex + "0000010";
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when others => StepIndex <= StepIndex - "0000001";
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end case;
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State <= State + 1;
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when 19 =>
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if (StepIndex = "1111111") then
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StepIndex <= (others => '0');
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elsif (StepIndex > "1011000") then
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StepIndex <= "1011000";
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end if;
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--diff is always positive, it becomes negative if we substract Pred - diff == Pred + (-diff)
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--so the sign of diff is marked by ADPCM_sample2(3)
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if (PredictedValue(15) = '0' and ADPCM_sample2(3) = '0' and AdderSub16(15) = '1') then --both positives result in negative?
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PredictedValue <= '0' & (14 downto 0 => '1'); --positive overflow -> set biggest positive
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elsif (PredictedValue(15) = '1' and ADPCM_sample2(3) = '1' and AdderSub16(15) = '0') then --both negatives result positive?
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PredictedValue <= '1' & (14 downto 0 => '0'); --negative overflow -> set biggest negative
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else --one positive, the other negative (overflow not possible)
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PredictedValue <= AdderSub16(15 downto 0);
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end if;
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State <= 0; --go wait for new sample ready
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when others =>
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State <= 0;
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end case;
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ADPCM_sample <= ADPCM_sample2;
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end if;
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end process;
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end Behavioral;
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