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----------------------------------------------------------------------------------
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-- Company: VISENGI S.L. (www.visengi.com)
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-- Engineer: Victor Lopez Lorenzo (victor.lopez (at) visengi (dot) com)
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--
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-- Create Date: 19:34:36 04/November/2008
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-- Project Name: IMA ADPCM Encoder
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-- Tool versions: Xilinx ISE 9.2i
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-- Description:
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--
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-- Description: This project features a full-hardware sound compressor using the well known algorithm IMA ADPCM.
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-- The core acts as a slave WISHBONE device. The output is perfectly compatible with any sound player
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-- with the IMA ADPCM codec (included by default in every Windows). Includes a testbench that takes
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-- an uncompressed PCM 16 bits Mono WAV file and outputs an IMA ADPCM compressed WAV file.
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-- Compression ratio is fixed for IMA-ADPCM, being 4:1.
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--
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--
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-- LICENSE TERMS: GNU GENERAL PUBLIC LICENSE Version 3
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--
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-- That is you may use it only in NON-COMMERCIAL projects.
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-- You are only required to include in the copyrights/about section
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-- that your system contains a "IMA ADPCM Encoder (C) VISENGI S.L. under GPL license"
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-- This holds also in the case where you modify the core, as the resulting core
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-- would be a derived work.
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-- Also, we would like to know if you use this core in a project of yours, just an email will do.
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--
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-- Please take good note of the disclaimer section of the GPL license, as we don't
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-- take any responsability for anything that this core does.
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----------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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--
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-- static const uint16_t IMA_ADPCMStepTable[89] =
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-- {
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-- 7, 8, 9, 10, 11, 12, 13, 14,
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-- 16, 17, 19, 21, 23, 25, 28, 31,
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-- 34, 37, 41, 45, 50, 55, 60, 66,
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-- 73, 80, 88, 97, 107, 118, 130, 143,
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-- 157, 173, 190, 209, 230, 253, 279, 307,
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-- 337, 371, 408, 449, 494, 544, 598, 658,
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-- 724, 796, 876, 963, 1060, 1166, 1282, 1411,
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-- 1552, 1707, 1878, 2066, 2272, 2499, 2749, 3024,
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-- 3327, 3660, 4026, 4428, 4871, 5358, 5894, 6484,
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-- 7132, 7845, 8630, 9493,10442,11487,12635,13899,
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-- 15289,16818,18500,20350,22385,24623,27086,29794,
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-- 32767
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-- };
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--
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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use ieee.numeric_std.all;
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entity IMA_adpcm_steptable_rom is
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generic (ROMADDR_W : integer := 7;
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ROMDATA_W : integer := 15);
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port(
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addr0 : in STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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clk : in STD_LOGIC;
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datao0 : out STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0));
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end IMA_adpcm_steptable_rom;
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architecture RTL of IMA_adpcm_steptable_rom is
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type ROM_TYPE is array (0 to 2**ROMADDR_W-1)
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of STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
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constant rom : ROM_TYPE :=
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(
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"000000000000111",
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"000000000001000",
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"000000000001001",
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"000000000001010",
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"000000000001011",
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"000000000001100",
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"000000000001101",
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"000000000001110",
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"000000000010000",
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"000000000010001",
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"000000000010011",
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"000000000010101",
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"000000000010111",
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"000000000011001",
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"000000000011100",
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"000000000011111",
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"000000000100010",
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"000000000100101",
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"000000000101001",
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"000000000101101",
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"000000000110010",
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"000000000110111",
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"000000000111100",
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"000000001000010",
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"000000001001001",
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"000000001010000",
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"000000001011000",
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"000000001100001",
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"000000001101011",
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"000000001110110",
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"000000010000010",
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"000000010001111",
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"000000010011101",
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"000000010101101",
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"000000010111110",
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"000000011010001",
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"000000011100110",
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"000000011111101",
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"000000100010111",
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"000000100110011",
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"000000101010001",
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"000000101110011",
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"000000110011000",
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"000000111000001",
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"000000111101110",
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"000001000100000",
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"000001001010110",
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"000001010010010",
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"000001011010100",
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"000001100011100",
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"000001101101100",
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"000001111000011",
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"000010000100100",
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"000010010001110",
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"000010100000010",
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"000010110000011",
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"000011000010000",
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"000011010101011",
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"000011101010110",
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"000100000010010",
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"000100011100000",
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"000100111000011",
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"000101010111101",
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"000101111010000",
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"000110011111111",
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"000111001001100",
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"000111110111010",
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"001000101001100",
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"001001100000111",
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"001010011101110",
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"001011100000110",
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"001100101010100",
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"001101111011100",
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"001111010100101",
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"010000110110110",
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"010010100010101",
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"010100011001010",
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"010110011011111",
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"011000101011011",
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"011011001001011",
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"011101110111001",
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"100000110110010",
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"100100001000100",
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"100111101111110",
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"101011101110001",
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"110000000101111",
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"110100111001110",
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"111010001100010",
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"111111111111111",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000",
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"000000000000000"
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);
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signal addr_reg0 : STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
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begin
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datao0 <= rom( TO_INTEGER(UNSIGNED(addr_reg0)) );
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process(clk)
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begin
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if clk = '1' and clk'event then
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addr_reg0 <= addr0;
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end if;
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end process;
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end RTL;
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No newline at end of file
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No newline at end of file
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