| Line 204... |
Line 204... |
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byte_we : in std_logic_vector(3 downto 0);
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byte_we : in std_logic_vector(3 downto 0);
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data_wr : in std_logic_vector(31 downto 0);
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data_wr : in std_logic_vector(31 downto 0);
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mem_wait : out std_logic;
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mem_wait : out std_logic;
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cache_ready : out std_logic;
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cache_enable : in std_logic;
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cache_enable : in std_logic;
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ic_invalidate : in std_logic;
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ic_invalidate : in std_logic;
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unmapped : out std_logic;
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unmapped : out std_logic;
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-- interface to FPGA i/o devices
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-- interface to FPGA i/o devices
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| Line 258... |
Line 259... |
subtype t_wait_state_counter is std_logic_vector(2 downto 0);
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subtype t_wait_state_counter is std_logic_vector(2 downto 0);
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-- State machine ----------------------------------------------------
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-- State machine ----------------------------------------------------
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type t_cache_state is (
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type t_cache_state is (
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cache_reset, -- Between reset and 1st code refill,
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idle, -- Cache is hitting, control machine idle
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idle, -- Cache is hitting, control machine idle
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-- Code refill --------------------------------------------------
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-- Code refill --------------------------------------------------
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code_refill_bram_0, -- pc in bram_rd_addr
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code_refill_bram_0, -- pc in bram_rd_addr
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code_refill_bram_1, -- op in bram_rd
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code_refill_bram_1, -- op in bram_rd
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| Line 387... |
Line 389... |
-- code_miss for accesses to UNCACHED areas OR with cache disabled
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-- code_miss for accesses to UNCACHED areas OR with cache disabled
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signal code_miss_uncached : std_logic;
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signal code_miss_uncached : std_logic;
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-- '1' when the I-cache state machine stalls the pipeline (mem_wait)
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-- '1' when the I-cache state machine stalls the pipeline (mem_wait)
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signal code_wait : std_logic;
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signal code_wait : std_logic;
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-- D-cache ----------------------------------------------------------
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-- D-cache ----------------------------------------------------------
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subtype t_data_tag is std_logic_vector(DATA_TAG_SIZE+1-1 downto 0);
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subtype t_data_tag is std_logic_vector(DATA_TAG_SIZE+1-1 downto 0);
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type t_data_tag_table is array(CACHE_SIZE-1 downto 0) of t_data_tag;
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type t_data_tag_table is array(CACHE_SIZE-1 downto 0) of t_data_tag;
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type t_data_line_table is array((CACHE_SIZE*LINE_SIZE)-1 downto 0) of t_word;
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type t_data_line_table is array((CACHE_SIZE*LINE_SIZE)-1 downto 0) of t_word;
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| Line 466... |
Line 469... |
cache_state_machine_reg:
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cache_state_machine_reg:
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process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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if reset='1' then
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if reset='1' then
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ps <= idle;
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ps <= cache_reset;
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else
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else
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ps <= ns;
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ps <= ns;
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end if;
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end if;
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end if;
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end if;
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end process cache_state_machine_reg;
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end process cache_state_machine_reg;
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| Line 483... |
Line 486... |
data_wr_attr.mem_type, data_rd_attr.mem_type, code_rd_attr.mem_type,
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data_wr_attr.mem_type, data_rd_attr.mem_type, code_rd_attr.mem_type,
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ws_wait_done, code_refill_ctr, data_refill_ctr,
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ws_wait_done, code_refill_ctr, data_refill_ctr,
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write_pending, read_pending)
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write_pending, read_pending)
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begin
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begin
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case ps is
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case ps is
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when idle =>
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-- The cache will remain in 'cache_reset' state until the first code miss,
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-- at which time the state machine proceeds as usual.
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-- The only difference between states idle and cache_reset is that in
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-- cache_reset the output cache_ready is '0', which will prevent the CPU
|
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-- from loading its IR with the cache output -- which is known invalid.
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when idle | cache_reset =>
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if code_miss='1' then
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if code_miss='1' then
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case code_rd_attr.mem_type is
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case code_rd_attr.mem_type is
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when MT_BRAM => ns <= code_refill_bram_0;
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when MT_BRAM => ns <= code_refill_bram_0;
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when MT_SRAM_16B => ns <= code_refill_sram_0;
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when MT_SRAM_16B => ns <= code_refill_sram_0;
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when MT_SRAM_8B => ns <= code_refill_sram8_0;
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when MT_SRAM_8B => ns <= code_refill_sram8_0;
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| Line 1416... |
Line 1425... |
'1' when data_read_io_0,
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'1' when data_read_io_0,
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-- In any other state, stall CPU only if there's a RD/WR pending.
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-- In any other state, stall CPU only if there's a RD/WR pending.
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read_pending or write_pending when others;
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read_pending or write_pending when others;
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|
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-- The cache will be ready only after the first code refill.
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-- This will prevent the CPU from loading junk into the IR.
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with ps select cache_ready <=
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'0' when cache_reset,
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'1' when others;
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end architecture direct;
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end architecture direct;
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No newline at end of file
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No newline at end of file
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