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-- IOTA Pearl Diver VHDL Port
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--
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-- 2018 by Thomas Pototschnig <microengineer18@gmail.com,
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-- http://microengineer.eu
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-- discord: pmaxuw#8292
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--
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-- Permission is hereby granted, free of charge, to any person obtaining
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-- a copy of this software and associated documentation files (the
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-- "Software"), to deal in the Software without restriction, including
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-- without limitation the rights to use, copy, modify, merge, publish,
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-- distribute, sublicense, and/or sell copies of the Software, and to
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-- permit persons to whom the Software is furnished to do so, subject to
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-- the following conditions:
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--
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-- The above copyright notice and this permission notice shall be
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-- included in all copies or substantial portions of the Software.
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--
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-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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-- EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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-- MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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-- NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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-- LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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-- OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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-- WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWAR
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library IEEE;
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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);
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);
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end;
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end;
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architecture beh of de1 is
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architecture beh of de1 is
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signal nreset : std_logic;
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signal pll_clk : std_logic;
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signal pll_clk : std_logic;
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signal pll_reset : std_logic := '0';
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signal pll_reset : std_logic := '0';
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signal pll_locked : std_logic;
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signal pll_locked : std_logic;
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signal spi_data_tx : std_logic_vector(31 downto 0);
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signal spi_data_tx : std_logic_vector(31 downto 0);
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signal spi_data_rx : std_logic_vector(31 downto 0);
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signal spi_data_rx : std_logic_vector(31 downto 0);
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signal spi_data_rx_en : std_logic;
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signal spi_data_rx_en : std_logic;
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signal spi_data_strobe : std_logic;
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signal pll_slow : std_logic;
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signal pll_slow : std_logic;
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component spi_slave
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component spi_slave
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port
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port
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mosi : in std_logic;
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mosi : in std_logic;
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miso : out std_logic;
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miso : out std_logic;
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sck : in std_logic;
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sck : in std_logic;
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ss : in std_logic;
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ss : in std_logic;
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data_strobe : in std_logic;
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data_rd : in std_logic_vector(31 downto 0);
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data_rd : in std_logic_vector(31 downto 0);
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data_wr : out std_logic_vector(31 downto 0);
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data_wr : out std_logic_vector(31 downto 0);
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data_wren : out std_logic
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data_wren : out std_logic
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reset : in std_logic;
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reset : in std_logic;
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spi_data_rx : in std_logic_vector(31 downto 0);
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spi_data_rx : in std_logic_vector(31 downto 0);
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spi_data_tx : out std_logic_vector(31 downto 0);
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spi_data_tx : out std_logic_vector(31 downto 0);
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spi_data_rxen : in std_logic;
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spi_data_rxen : in std_logic;
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spi_data_strobe : out std_logic;
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overflow : out std_logic;
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overflow : out std_logic;
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running : out std_logic;
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running : out std_logic;
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found : out std_logic
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found : out std_logic
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);
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);
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end component;
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end component;
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begin
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begin
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nreset <= not reset;
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pll0 : pll port map (
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pll0 : pll port map (
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areset => pll_reset,
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areset => pll_reset,
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inclk0 => CLOCK_50,
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inclk0 => CLOCK_50,
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c0 => pll_clk,
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c0 => pll_clk,
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c1 => pll_slow,
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c1 => pll_slow,
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);
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);
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spi0 : spi_slave port map (
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spi0 : spi_slave port map (
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clk => pll_slow,
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clk => pll_slow,
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reset => reset,
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reset => nreset,
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mosi => spi_mosi,
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mosi => spi_mosi,
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miso => spi_miso,
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miso => spi_miso,
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sck => spi_sck,
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sck => spi_sck,
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ss => spi_ss,
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ss => spi_ss,
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data_strobe => spi_data_strobe,
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data_rd => spi_data_tx,
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data_rd => spi_data_tx,
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data_wr => spi_data_rx,
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data_wr => spi_data_rx,
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data_wren => spi_data_rx_en
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data_wren => spi_data_rx_en
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);
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);
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curl0 : curl port map (
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curl0 : curl port map (
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clk => pll_clk,
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clk => pll_clk,
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reset => reset,
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reset => nreset,
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clk_slow => pll_slow,
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clk_slow => pll_slow,
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spi_data_rx => spi_data_rx,
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spi_data_rx => spi_data_rx,
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spi_data_tx => spi_data_tx,
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spi_data_tx => spi_data_tx,
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spi_data_rxen => spi_data_rx_en,
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spi_data_rxen => spi_data_rx_en,
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spi_data_strobe => spi_data_strobe,
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overflow => led_overflow,
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overflow => led_overflow,
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running => led_running,
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running => led_running,
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found => led_found
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found => led_found
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);
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);
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