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https://opencores.org/ocsvn/iso7816_3_master/iso7816_3_master/trunk
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`timescale 1ns / 1ps
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`timescale 1ns / 1ps
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`default_nettype none
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`default_nettype none
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Author: Sebastien Riou
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// Engineer:
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// Creation date: 17:16:40 01/09/2011
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//
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//
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// Create Date: 17:16:40 01/09/2011
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// Last change date: $LastChangedDate: 2011-01-29 11:41:01 +0100 (Sat, 29 Jan 2011) $
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// Design Name:
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// Last changed by: $LastChangedBy: acapola $
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// Module Name: Iso7816_3_Master
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// Last revision: $LastChangedRevision: 10 $
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// Project Name:
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// Head URL: $HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/sources/Iso7816_3_Master.v $
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//
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//////////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////
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module Iso7816_3_Master(
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module Iso7816_3_Master(
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input wire nReset,
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input wire nReset,
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input wire clk,
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input wire clk,
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