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`timescale 1ns / 1ps
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/*
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Author: Sebastien Riou (acapola)
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Creation date: 22:22:43 01/10/2011
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$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
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$LastChangedBy: acapola $
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$LastChangedRevision: 11 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/DummyCard.v $
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`default_nettype none
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`default_nettype none
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////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 22:22:43 01/10/2011
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// Design Name: HalfDuplexUartIf
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// Module Name: dummyCard.v
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// Project Name: Uart
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: HalfDuplexUartIf
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module DummyCard(
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module DummyCard(
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input wire isoReset,
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input wire isoReset,
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input wire isoClk,
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input wire isoClk,
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input wire isoVdd,
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input wire isoVdd,
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end else if(sendAtr) begin
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end else if(sendAtr) begin
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sendAtr<=1'b0;
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sendAtr<=1'b0;
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sendHexBytes("3B00");
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sendHexBytes("3B00");
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waitEndOfTx;
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waitEndOfTx;
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end else begin
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end else begin
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//get tpdu
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//get CLA
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for(i=0;i<5;i=i+1)
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receiveByte(tpduHeader[CLA_I+:8]);
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//get INS~P2 or PPS
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for(i=1;i<4;i=i+1)
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receiveByte(tpduHeader[(CLA_I-(i*8))+:8]);
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receiveByte(tpduHeader[(CLA_I-(i*8))+:8]);
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if(8'hFF==tpduHeader[CLA_I+:8]) begin
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//support only PPS8 for the time being
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if(32'hFF789778==tpduHeader[7+CLA_I:P2_I]) begin
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sendHexBytes("FF789778");
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waitEndOfTx;
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cyclesPerEtu <= 13'd8-1'b1;
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end
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end else begin
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//tpdu: get P3
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receiveByte(tpduHeader[P3_I+:8]);
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//dispatch
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//dispatch
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case(tpduHeader[7+CLA_I:P2_I])
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case(tpduHeader[7+CLA_I:P2_I])
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32'h000C0000: writeBufferCmd;
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32'h000C0000: writeBufferCmd;
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32'h000A0000: readBufferCmd;
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32'h000A0000: readBufferCmd;
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default: sendHexBytes("6986");//sendWord(16'h6986);
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default: sendHexBytes("6986");//sendWord(16'h6986);
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endcase
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endcase
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end
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end
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end
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end
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end
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endmodule
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endmodule
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`default_nettype wire
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