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/*
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/*
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Author: Sebastien Riou (acapola)
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Author: Sebastien Riou (acapola)
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Creation date: 22:22:43 01/10/2011
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Creation date: 22:22:43 01/10/2011
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$LastChangedDate: 2011-02-18 15:23:07 +0100 (Fri, 18 Feb 2011) $
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$LastChangedDate: 2011-03-07 14:17:52 +0100 (Mon, 07 Mar 2011) $
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$LastChangedBy: acapola $
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$LastChangedBy: acapola $
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$LastChangedRevision: 17 $
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$LastChangedRevision: 18 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/iso7816_3_t0_analyzer.v $
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This file is under the BSD licence:
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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Copyright (c) 2011, Sebastien Riou
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//integer COM_errorCnt;
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//integer COM_errorCnt;
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//wire txPending=1'b0;
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//wire txPending=1'b0;
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//wire txRun=1'b0;
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//wire txRun=1'b0;
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wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;
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wire rxRun, rxStartBit, overrunErrorFlag, frameErrorFlag, bufferFull;
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assign overrunErrorFlag = overrunError;
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//assign overrunErrorFlag = overrunError;
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assign frameErrorFlag = frameError;
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assign frameErrorFlag = frameError;
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wire [7:0] rxData;
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wire [7:0] rxData;
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reg ackFlags;
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reg ackFlags;
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always @(*) comOnGoing = rxRun|rxStartBit;
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always @(*) comOnGoing = rxRun|rxStartBit;
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always @(posedge clk, negedge rxCore_nReset) begin
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always @(posedge clk, negedge rxCore_nReset) begin
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if(~rxCore_nReset) begin
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if(~rxCore_nReset) begin
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safeClocksPerBit<=clocksPerBit;
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safeClocksPerBit<={CLOCK_PER_BIT_WIDTH{1'b0}};
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end else if(endOfRx|~comOnGoing) begin
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end else if(endOfRx|~comOnGoing) begin
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safeClocksPerBit<=clocksPerBit;
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safeClocksPerBit<=clocksPerBit;
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end
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end
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end
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end
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end else if((32'b1==bytesCnt) & tsReceived) begin
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end else if((32'b1==bytesCnt) & tsReceived) begin
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lastByte<=ts;
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lastByte<=ts;
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end
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end
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end
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end
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reg ppsValidSoFar;
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reg ppsValidSoFar;
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reg ppsAccepted;
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//reg ppsAccepted;
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wire ppsDataMatch = (tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]==dataOut);
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wire ppsDataMatch = (tpduHeader[(CLA_I-(tempBytesCnt*8))+:8]==dataOut);
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wire [3:0] earlyAtrK = (4'h0==tdiCnt) ? dataOut[3:0] : atrK;
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wire [3:0] earlyAtrK = (4'h0==tdiCnt) ? dataOut[3:0] : atrK;
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always @(posedge isoClk, negedge rxCore_nReset) begin
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always @(posedge isoClk, negedge rxCore_nReset) begin
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if(~rxCore_nReset) begin
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if(~rxCore_nReset) begin
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ppsValidSoFar<=1'b0;
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ppsValidSoFar<=1'b0;
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ppsAccepted<=1'b0;
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//ppsAccepted<=1'b0;
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fiCode<=4'b0001;
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fiCode<=4'b0001;
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diCode<=4'b0001;
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diCode<=4'b0001;
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useT0<=1'b1;
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useT0<=1'b1;
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useT1<=1'b0;
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useT1<=1'b0;
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useT15<=1'b0;
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useT15<=1'b0;
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if(tempBytesCnt+1==nIfBytes) begin //TDi bytes
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if(tempBytesCnt+1==nIfBytes) begin //TDi bytes
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if(4'h0==tdiCnt) begin//this is T0
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if(4'h0==tdiCnt) begin//this is T0
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atrK <= dataOut[3:0];
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atrK <= dataOut[3:0];
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end
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end
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tempBytesCnt <= 2'h0;
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tempBytesCnt <= 2'h0;
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tdiStruct <= {tdiCnt+1,dataOut};
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tdiStruct <= {tdiCnt+1'b1,dataOut};
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if(12'h0=={dataOut,atrK}) begin
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if(12'h0=={dataOut,atrK}) begin
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atrCompleted <= 1'b1;
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atrCompleted <= 1'b1;
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{waitCardTx,waitTermTx}<=2'b01;
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{waitCardTx,waitTermTx}<=2'b01;
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end
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end
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if((1'b0==tdiStruct[7]) |//we just received the last interface byte
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if((1'b0==tdiStruct[7]) |//we just received the last interface byte
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fsmState <= ATR_TDI;
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fsmState <= ATR_TDI;
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end
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end
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end else begin //TA, TB or TC bytes
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end else begin //TA, TB or TC bytes
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//TODO: get relevant info
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//TODO: get relevant info
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tempBytesCnt <= tempBytesCnt+1;
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tempBytesCnt <= tempBytesCnt+1'b1;
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end
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end
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end
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end
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end
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end
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ATR_HISTORICAL: begin
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ATR_HISTORICAL: begin
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if(endOfRx) begin
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if(endOfRx) begin
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atrCompleted <= 1'b1;
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atrCompleted <= 1'b1;
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{waitCardTx,waitTermTx}<=2'b10;
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{waitCardTx,waitTermTx}<=2'b10;
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fsmState <= T0_HEADER;
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fsmState <= T0_HEADER;
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end
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end
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end else begin
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end else begin
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tempBytesCnt <= tempBytesCnt+1;
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tempBytesCnt <= tempBytesCnt+1'b1;
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end
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end
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end
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end
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end
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end
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ATR_TCK: begin
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ATR_TCK: begin
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if(endOfRx) begin
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if(endOfRx) begin
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if(3==tempBytesCnt) begin//support only 4 byte PPS
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if(3==tempBytesCnt) begin//support only 4 byte PPS
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tempBytesCnt <= 8'h0;
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tempBytesCnt <= 8'h0;
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fsmState <= T0_PPS_RESPONSE;
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fsmState <= T0_PPS_RESPONSE;
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{waitCardTx,waitTermTx}<=2'b10;
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{waitCardTx,waitTermTx}<=2'b10;
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ppsValidSoFar<=1'b1;
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ppsValidSoFar<=1'b1;
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ppsAccepted<=1'b0;
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//ppsAccepted<=1'b0;
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end else begin
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end else begin
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tempBytesCnt <= tempBytesCnt+1;
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tempBytesCnt <= tempBytesCnt+1'b1;
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end
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end
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end
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end
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end
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end
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T0_PPS_RESPONSE: begin
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T0_PPS_RESPONSE: begin
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if(3==tempBytesCnt) begin//support only 4 byte PPS
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if(3==tempBytesCnt) begin//support only 4 byte PPS
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useT1<=1'b0;
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useT1<=1'b0;
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useT15<=1'b0;
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useT15<=1'b0;
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end
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end
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endcase
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endcase
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end else begin
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end else begin
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tempBytesCnt <= tempBytesCnt+1;
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tempBytesCnt <= tempBytesCnt+1'b1;
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end
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end
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end
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end
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end
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end
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T0_HEADER_TPDU: begin
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T0_HEADER_TPDU: begin
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if(endOfRx) begin
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if(endOfRx) begin
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if(4==tempBytesCnt) begin
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if(4==tempBytesCnt) begin
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tempBytesCnt <= 8'h0;
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tempBytesCnt <= 8'h0;
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fsmState <= T0_PB;
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fsmState <= T0_PB;
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{waitCardTx,waitTermTx}<=2'b10;
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{waitCardTx,waitTermTx}<=2'b10;
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end else begin
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end else begin
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tempBytesCnt <= tempBytesCnt+1;
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tempBytesCnt <= tempBytesCnt+1'b1;
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end
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end
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end
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end
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end
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end
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T0_PB: begin
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T0_PB: begin
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if(endOfRx) begin
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if(endOfRx) begin
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Line 401... |
end
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end
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T0_NACK_DATA: begin
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T0_NACK_DATA: begin
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if(endOfRx) begin
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if(endOfRx) begin
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fsmState <= T0_PB;
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fsmState <= T0_PB;
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{waitCardTx,waitTermTx}<=2'b10;
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{waitCardTx,waitTermTx}<=2'b10;
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tempBytesCnt <= tempBytesCnt+1;
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tempBytesCnt <= tempBytesCnt+1'b1;
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end
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end
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end
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end
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T0_SW1: begin
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T0_SW1: begin
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if(endOfRx) begin
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if(endOfRx) begin
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//TODO:check != 60 but equal to 6x or 9x
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//TODO:check != 60 but equal to 6x or 9x
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Line 424... |
if(tempBytesCnt==(tpduHeader[P3_I+:8]-1)) begin
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if(tempBytesCnt==(tpduHeader[P3_I+:8]-1)) begin
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tempBytesCnt <= 0;
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tempBytesCnt <= 0;
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fsmState <= T0_SW1;
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fsmState <= T0_SW1;
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{waitCardTx,waitTermTx}<=2'b10;
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{waitCardTx,waitTermTx}<=2'b10;
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end else begin
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end else begin
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tempBytesCnt <= tempBytesCnt+1;
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tempBytesCnt <= tempBytesCnt+1'b1;
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end
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end
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end
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end
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end
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end
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endcase
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endcase
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end
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end
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