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`timescale 1ns / 1ps
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/*
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Author: Sebastien Riou (acapola)
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Creation date: 22:16:42 01/10/2011
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$LastChangedDate: 2011-01-29 13:16:17 +0100 (Sat, 29 Jan 2011) $
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$LastChangedBy: acapola $
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$LastChangedRevision: 11 $
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$HeadURL: file:///svn/iso7816_3_master/iso7816_3_master/trunk/test/tbIso7816_3_Master.v $
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This file is under the BSD licence:
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Copyright (c) 2011, Sebastien Riou
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
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Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
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Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
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The names of contributors may not be used to endorse or promote products derived from this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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`default_nettype none
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`default_nettype none
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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// Company:
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// Engineer: Sebastien Riou
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//
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// Create Date: 22:16:42 01/10/2011
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// Design Name: Iso7816_3_Master
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// Module Name: tbIso7816_3_Master.v
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// Project Name: Uart
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// Target Device:
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// Tool versions:
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// Description:
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//
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// Verilog Test Fixture created by ISE for module: Iso7816_3_Master
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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////////////////////////////////////////////////////////////////////////////////
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module tbIso7816_3_Master;
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module tbIso7816_3_Master;
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parameter CLK_PERIOD = 10;//should be %2
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parameter CLK_PERIOD = 10;//should be %2
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// Inputs
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// Inputs
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reg nReset;
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reg nReset;
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.bytesCnt(spy_bytesCnt)
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.bytesCnt(spy_bytesCnt)
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);
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);
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integer tbErrorCnt;
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integer tbErrorCnt;
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reg tbTestSequenceDone;
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initial begin
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initial begin
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// Initialize Inputs
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// Initialize Inputs
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tbErrorCnt=0;
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COM_errorCnt=0;
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COM_errorCnt=0;
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nReset = 0;
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nReset = 0;
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clk = 0;
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clk = 0;
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clkPerCycle = 0;
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clkPerCycle = 0;
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startActivation = 0;
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startActivation = 0;
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while((txRun===1'b1)||(rxRun===1'b1)||(rxStartBit===1'b1)) begin
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while((txRun===1'b1)||(rxRun===1'b1)||(rxStartBit===1'b1)) begin
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@(posedge clk);
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@(posedge clk);
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end
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end
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@(posedge clk);
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@(posedge clk);
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end
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end
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$display("Two cycle pause in communication detected, stop simulation, time=",$time);
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if(1'b1!==tbTestSequenceDone) begin
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$display("ERROR: Two cycle pause in communication detected, stop simulation, time=",$time);
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#(CLK_PERIOD*372*12);
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#(CLK_PERIOD*372*12);
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$finish;
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$finish;
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end
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end
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end
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//T=0 tpdu stimuli
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//T=0 tpdu stimuli
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initial begin
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initial begin
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//receiveAndCheckByte(8'h3B);
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tbTestSequenceDone=1'b0;
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//receiveAndCheckByte(8'h00);
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receiveAndCheckHexBytes("3B00");
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receiveAndCheckHexBytes("3B00");
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sendHexBytes("000C000001");
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sendHexBytes("000C000001");
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//receiveAndCheckByte(8'h0C);
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receiveAndCheckHexBytes("0C");
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receiveAndCheckHexBytes("0C");
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sendHexBytes("55");
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sendHexBytes("55");
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//receiveAndCheckByte(8'h90);
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//receiveAndCheckByte(8'h00);
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receiveAndCheckHexBytes("9000");
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receiveAndCheckHexBytes("9000");
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tbTestSequenceDone=1'b1;
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$display("SUCCESS: test sequence completed.");
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#(CLK_PERIOD*372*12);
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$finish;
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end
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end
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initial begin
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initial begin
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// timeout
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// timeout
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#10000000;
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#10000000;
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tbErrorCnt=tbErrorCnt+1;
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tbErrorCnt=tbErrorCnt+1;
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$finish;
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$finish;
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end
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end
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always
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always
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#(CLK_PERIOD/2) clk = ! clk;
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#(CLK_PERIOD/2) clk = ! clk;
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endmodule
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endmodule
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`default_nettype wire
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No newline at end of file
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No newline at end of file
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