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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.library ieee;
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-- along with JART (Just Another Ray Tracer). If not, see <http://www.gnu.org/licenses/>.library ieee;
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-- Unitary ray vector Y component integrator. In a memory block of 1x16384 bits, it is stored the FY' that represents the first derivate of FY, this function is the Y function along any horizontal line in the image.
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-- Ray Generator.....
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-- The derivative is stored in this way: logic 0 means a 0 pendant and logic 1 means a -1 pendant. So a counter with enable / disable control it is everything we need, and of course a load input to represent the initial value added to the integral.
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-- The entity synthesizes 4 simmetrical rays each clock. The ena signal enables/disables the ray production.
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-- The Ray Generator starts by generating after the first clock's rising edge with the ena signal set.
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-- The first four rays generated are the Rays passing through the center of the screen, in the 320x200 screen these rays are : (159,99)(160,99)(159,100)(160,100), after those rays the next four rays are (158,99)(161,99)(158,100)(161,100).
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_signed.all;
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use ieee.std_logic_signed.all;
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use work.powerGrid.all;
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use work.powerGrid.all;
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entity yu is
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entity yu is
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generic (
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generic (
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VALSTARTX : integer := 34;
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VALSTARTY : integer := 1023;
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VALSTARTZ : integer := 9;
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TOP : integer := 1024; -- Define the max counting number.. the number must be expressed as 2 power, cause the range of counting is going to be defined as TOP-1 downto TOP/2.
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TOP : integer := 1024; -- Define the max counting number.. the number must be expressed as 2 power, cause the range of counting is going to be defined as TOP-1 downto TOP/2.
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-- However this is going to be by now, cause in the future the ray generation will GO on for higher resolution images , and perhaps it would be required a more extended range for the yu component.
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-- However this is going to be by now, cause in the future the ray generation will GO on for higher resolution images , and perhaps it would be required a more extended range for the yu component.
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SCREENW : integer := 320 -- resolution width is 320
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SCREENW : integer := 320 -- resolution width is 320
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);
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);
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port (
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port (
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clk,rst,ena : in std_logic;
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clk,rst,ena : in std_logic;
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lineDone : out std_logic; -- Finished image row. once a hundred and sixty times....
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lineDone : out std_logic; -- Finished image row. once a hundred and sixty times....
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ypos : out integer range TOP/2 to TOP-1
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ocntr : out integer range 0 to SCREENW/2;
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-- ocntr : out integer range 0 to SCREENW/2
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ypos : out integer range TOP/2 to TOP-1;
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zpos : out integer range -TOP to TOP-1;
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zneg : out integer range -TOP to TOP-1;
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xpos : out integer range -TOP to TOP-1;
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xneg : out integer range -TOP to TOP-1
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);
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);
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end entity;
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end entity;
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architecture rtl of yu is
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architecture rtl of yu is
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-- 1x16384 bits, true dual port, ROM Memory declaration.
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-- 1x16384 bits, true dual port, ROM Memory declaration.
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-- This memory uses 2 cycles.. a memory fetch cycle and a data to q memory cycle.
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-- This memory uses 2 cycles.. a memory fetch cycle and a data to q memory cycle.
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component yurom
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component yurom
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port
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port
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(
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(
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);
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);
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end component;
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end component;
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constant linefeed : integer range 0 to (SCREENW/2) := (SCREENW/2)-2;
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constant linefeed : integer range 0 to (SCREENW/2) := (SCREENW/2)-4;
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-- Support signals.
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-- Support signals.
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signal s1addf0 : std_logic_vector (13 downto 0); -- The function 0 is the function of the y component derivative.
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signal s1addf0 : std_logic_vector (13 downto 0); -- The function 0 is the function of the y component derivative.
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signal s1addf1 : std_logic_vector (13 downto 0); -- The function 1 is the function of the y component integration curve initial constant.
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signal s1addf1 : std_logic_vector (13 downto 0); -- The function 1 is the function of the y component integration curve initial constant.
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signal sf0 : std_logic_vector (0 downto 0); -- Derivative function
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signal sf0 : std_logic_vector (0 downto 0); -- Derivative function
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signal sf1 : std_logic_vector (0 downto 0); -- Derivative curve, initial constant derivative function.
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signal sf1 : std_logic_vector (0 downto 0); -- Derivative curve, initial constant derivative function.
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signal cc : integer range 0 to SCREENW/2;
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signal cc : integer range 0 to SCREENW/2;
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signal f0 : integer range TOP/2 to TOP-1;
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signal fy : integer range TOP/2 to TOP-1;
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signal pivotCol,pivotRow : std_logic;
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signal fz : integer range -TOP to TOP-1;
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signal fx : integer range -TOP to TOP-1;
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begin
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begin
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-- Connect f0, to the output.
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-- Connect fy, to the output.
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ypos <= f0;
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ypos <= fy;
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xpos <= fx;
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xneg <= -fx;
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zpos <= fz;
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zneg <= -fz;
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ocntr<= cc;
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derivate : yurom
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derivate : yurom
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port map (
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port map (
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address_a => s1addf0,
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address_a => s1addf0,
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address_b => s1addf1,
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address_b => s1addf1,
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);
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);
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integrationControl : process (clk,rst,ena)
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integrationControl : process (clk,rst,ena)
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variable f1 : integer range TOP/2 to TOP-1;
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variable f1 : integer range TOP/2 to TOP-1;
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begin
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begin
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if rst='0' then
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if rst='0' then
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f0<=TOP-1;
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fy<=TOP/2;
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f1:=TOP-1;
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f1:=VALSTARTY;
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lineDone<='0';
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fz<=VALSTARTZ-2;
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fx<=0;
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pivotCol <= '0';
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pivotRow <= '0';
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elsif rising_edge(clk) and ena='1' then
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elsif rising_edge(clk) and ena='1' then
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if cc=0 then
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if cc=(SCREENW/2)-1 then
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lineDone<='1';
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if sf1(0) ='1' then
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-- Y component
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f1 := f1 - 1;
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f1 := f1 - CONV_INTEGER('0'&sf1(0));
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end if;
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fy <= f1;
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f0 <= f1;
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-- X component
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fx <= VALSTARTX;
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-- Z component
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fz <= fz+2+CONV_INTEGER('0'&pivotRow); -- Beware of the sign!
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pivotRow <= not (pivotRow);
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else
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else
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lineDone<='0';
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if sf0(0) = '1' then
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f0 <= f0-1;
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end if;
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end if;
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-- Y Component
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fy <= fy-CONV_INTEGER('0'&sf0(0));
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-- X component
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fx <= fx+2+CONV_INTEGER('0'&pivotCol); -- Beware of the sign!
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pivotCol <= not(pivotCol);
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end if;
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end if;
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end if;
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counterControl : process (clk,rst,ena)
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counterControl : process (clk,rst,ena)
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begin
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begin
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if rst='0' then
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if rst='0' then
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cc<=0;
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cc<=SCREENW/2-1;
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lineDone<='0';
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elsif rising_edge(clk) and ena='1' then
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elsif rising_edge(clk) and ena='1' then
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if cc=(SCREENW/2)-1 then
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if cc=(SCREENW/2)-1 then
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lineDone<='1';
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cc<=0;
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cc<=0;
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else
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else
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lineDone<='0';
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cc<=cc+1;
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cc<=cc+1;
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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