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--
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-- Keyboard controller entity
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--
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-- The controller scans the columns, cols, by making a different column logic-0
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-- therefor the inputs have to be pull-up high. It processes the input, rows, and
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-- the pressed key to a corresponding scancode and giving an interrupt
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--
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-- Author: Wouter Wiggers
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-- Mail: w.a.wiggers@student.utwente.nl
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--
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------------------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.Constants.all;
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entity Keyboard_controller is
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port (reset, clk_in : in std_logic;
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clk_out : out std_logic;
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cols : in col;
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rows : out row;
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scan : out scancode;
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interrupt : out std_logic
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);
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end Keyboard_controller;
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architecture structure of Keyboard_controller is
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component Strober
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port (reset, clk : in std_logic;
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strobe : in std_logic;
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sample : in std_logic;
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env_col : in col;
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env_row : out row;
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sample_col : out col;
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sample_row_number : out row_number
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);
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end component;
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component Analyser
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port (reset, clk : in std_logic;
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analyse : in std_logic;
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store : in std_logic;
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debounced : out std_logic;
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keychanged : out std_logic;
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released : out std_logic;
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sample_col: in col;
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sample_row_number : in row_number;
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conv_col : out col_number;
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conv_row : out row_number
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);
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end component;
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component Producer
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port (reset, clk: in std_logic;
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produce : in std_logic;
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released : in std_logic;
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conv_col : in col_number;
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conv_row : in row_number;
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scanc : out scancode;
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interrupt : out std_logic
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);
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end component;
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component FSM
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port (reset, clk : in std_logic;
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strobe : out std_logic;
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sample : out std_logic;
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analyse : out std_logic;
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store : out std_logic;
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produce : out std_logic;
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release : out std_logic;
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debounced : in std_logic;
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keychanged : in std_logic; --keychange found
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keyreleased : in std_logic
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);
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end component;
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signal stb: std_logic;
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signal str: std_logic;
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signal sam: std_logic;
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signal ana: std_logic;
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signal pro: std_logic;
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signal rel: std_logic;
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signal deb: std_logic;
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signal keyc: std_logic;
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signal keyr: std_logic;
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signal col_sample : col;
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signal row_sample_number : row_number;
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signal col_conv : col_number;
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signal row_conv : row_number;
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signal clk : std_logic;
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begin
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-- divide by 512
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clockdiv: process
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variable count : std_logic_vector(8 downto 0);
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begin
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wait until rising_edge(clk_in);
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count := std_logic_vector(to_unsigned( (to_integer(unsigned(count)) + 1),9 ));
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clk <= count(8);
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end process;
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clk_out <= clk;
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strb: Strober port map (reset, clk, stb, sam, cols, rows, col_sample, row_sample_number);
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analys: Analyser port map (reset, clk, ana, str, deb, keyc, keyr, col_sample, row_sample_number, col_conv, row_conv);
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prod: Producer port map (reset, clk, pro, rel, col_conv, row_conv, scan, interrupt);
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finsm: FSM port map (reset, clk, stb, sam, ana, str, pro, rel , deb, keyc, keyr);
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end structure;
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