| Line 23... |
Line 23... |
//
|
//
|
EXECUTE:
|
EXECUTE:
|
begin
|
begin
|
state <= WRITEBACK;
|
state <= WRITEBACK;
|
case(opcode)
|
case(opcode)
|
`MISC:
|
|
case(func)
|
|
`STOP:
|
|
if (!sf) begin
|
|
vector <= `PRIVILEGE_VIOLATION;
|
|
state <= TRAP;
|
|
end
|
|
else begin
|
|
im <= imm[18:16];
|
|
tf <= imm[23];
|
|
sf <= imm[21];
|
|
clk_en <= 1'b0;
|
|
state <= IFETCH;
|
|
end
|
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endcase
|
|
`R:
|
`R:
|
begin
|
begin
|
case(func)
|
case(func)
|
`ABS: res <= a[31] ? -a : a;
|
`ABS: res <= a[31] ? -a : a;
|
`SGN: res <= a[31] ? 32'hFFFFFFFF : |a;
|
`SGN: res <= a[31] ? 32'hFFFFFFFF : |a;
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`NEG: res <= -a;
|
`NEG: res <= -a;
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`NOT: res <= ~a;
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`NOT: res <= ~a;
|
`EXTB: res <= {{24{a[7]}},a[7:0]};
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`EXTB: res <= {{24{a[7]}},a[7:0]};
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`EXTH: res <= {{16{a[15]}},a[15:0]};
|
`EXTH: res <= {{16{a[15]}},a[15:0]};
|
default: res <= 32'd0;
|
`MFSPR:
|
endcase
|
casex(ir[25:21])
|
case(func)
|
5'b00xxx: res <= GetCr(ir[23:21]);
|
`EXEC:
|
5'b01000: res <= cr;
|
begin
|
5'b01001: res <= usp;
|
ir <= a;
|
5'b01010:
|
Rn <= a[25:21];
|
if (!sf) begin
|
state <= REGFETCHA;
|
vector <= `PRIVILEGE_VIOLATION;
|
|
state <= TRAP;
|
end
|
end
|
`MOV_CRn2CRn:
|
else begin
|
begin
|
res <= im;
|
state <= IFETCH;
|
|
case(ir[18:16])
|
|
3'd0: cr0 <= GetCr(ir[23:21]);
|
|
3'd1: cr1 <= GetCr(ir[23:21]);
|
|
3'd2: cr2 <= GetCr(ir[23:21]);
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3'd3: cr3 <= GetCr(ir[23:21]);
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3'd4: cr4 <= GetCr(ir[23:21]);
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3'd5: cr5 <= GetCr(ir[23:21]);
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3'd6: cr6 <= GetCr(ir[23:21]);
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3'd7: cr7 <= GetCr(ir[23:21]);
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endcase
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end
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end
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`MOV_REG2CRn:
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5'b01111: res <= tick;
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endcase
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`MTSPR:
|
|
casex(ir[20:16])
|
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5'b00xxx: // MTSPR CRn,Rn
|
begin
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begin
|
|
state <= IFETCH;
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case(ir[18:16])
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case(ir[18:16])
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3'd0: cr0 <= a[3:0];
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3'd0: cr0 <= a[3:0];
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3'd1: cr1 <= a[3:0];
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3'd1: cr1 <= a[3:0];
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3'd2: cr2 <= a[3:0];
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3'd2: cr2 <= a[3:0];
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3'd3: cr3 <= a[3:0];
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3'd3: cr3 <= a[3:0];
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| Line 83... |
Line 63... |
3'd5: cr5 <= a[3:0];
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3'd5: cr5 <= a[3:0];
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3'd6: cr6 <= a[3:0];
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3'd6: cr6 <= a[3:0];
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3'd7: cr7 <= a[3:0];
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3'd7: cr7 <= a[3:0];
|
endcase
|
endcase
|
end
|
end
|
`MOV_CRn2REG:
|
5'b01000: // MTSPR CR,Rn
|
res <= GetCr(ir[23:21]);
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|
`MOV_CR2REG:
|
|
res <= cr;
|
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`MOV_REG2CR:
|
|
begin
|
begin
|
state <= IFETCH;
|
state <= IFETCH;
|
cr0 <= a[3:0];
|
cr0 <= a[3:0];
|
cr1 <= a[7:4];
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cr1 <= a[7:4];
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cr2 <= a[11:8];
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cr2 <= a[11:8];
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| Line 99... |
Line 75... |
cr4 <= a[19:16];
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cr4 <= a[19:16];
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cr5 <= a[23:20];
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cr5 <= a[23:20];
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cr6 <= a[27:24];
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cr6 <= a[27:24];
|
cr7 <= a[31:28];
|
cr7 <= a[31:28];
|
end
|
end
|
`MOV_REG2IM: if (!sf) begin
|
5'b01001: usp <= a; // MTSPR USP,Rn
|
|
5'b01010:
|
|
if (!sf) begin
|
vector <= `PRIVILEGE_VIOLATION;
|
vector <= `PRIVILEGE_VIOLATION;
|
state <= TRAP;
|
state <= TRAP;
|
end
|
end
|
else begin
|
else begin
|
im <= a[2:0];
|
im <= a[2:0];
|
state <= IFETCH;
|
state <= IFETCH;
|
end
|
end
|
`MOV_IM2REG: if (!sf) begin
|
endcase
|
vector <= `PRIVILEGE_VIOLATION;
|
`EXEC:
|
state <= TRAP;
|
begin
|
|
ir <= a;
|
|
Rn <= a[25:21];
|
|
state <= REGFETCHA;
|
end
|
end
|
else begin
|
`MOV_CRn2CRn:
|
res <= im;
|
begin
|
|
state <= IFETCH;
|
|
case(ir[18:16])
|
|
3'd0: cr0 <= GetCr(ir[23:21]);
|
|
3'd1: cr1 <= GetCr(ir[23:21]);
|
|
3'd2: cr2 <= GetCr(ir[23:21]);
|
|
3'd3: cr3 <= GetCr(ir[23:21]);
|
|
3'd4: cr4 <= GetCr(ir[23:21]);
|
|
3'd5: cr5 <= GetCr(ir[23:21]);
|
|
3'd6: cr6 <= GetCr(ir[23:21]);
|
|
3'd7: cr7 <= GetCr(ir[23:21]);
|
|
endcase
|
end
|
end
|
`MOV_USP2REG:
|
default: res <= 32'd0;
|
res <= usp;
|
|
`MOV_REG2USP:
|
|
usp <= a;
|
|
`MFTICK:
|
|
res <= tick;
|
|
endcase
|
endcase
|
end
|
end
|
`RR:
|
`RR:
|
begin
|
begin
|
case(func)
|
case(func)
|
`ADD: res <= a + b;
|
|
`SUB: res <= a - b;
|
`SUB: res <= a - b;
|
`CMP: res <= a - b;
|
|
`AND: res <= a & b;
|
`AND: res <= a & b;
|
|
`ANDC: res <= a & ~b;
|
`OR: res <= a | b;
|
`OR: res <= a | b;
|
|
`ORC: res <= a | ~b;
|
`EOR: res <= a ^ b;
|
`EOR: res <= a ^ b;
|
`NAND: res <= ~(a & b);
|
`NAND: res <= ~(a & b);
|
`NOR: res <= ~(a | b);
|
`NOR: res <= ~(a | b);
|
`ENOR: res <= ~(a ^ b);
|
`ENOR: res <= ~(a ^ b);
|
`SHL: res <= shlo[31: 0];
|
`SHL: res <= shlo[31: 0];
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| Line 154... |
Line 141... |
else if (func==`JSR_RR) begin
|
else if (func==`JSR_RR) begin
|
tgt <= a + b;
|
tgt <= a + b;
|
tgt[1:0] <= 2'b00;
|
tgt[1:0] <= 2'b00;
|
state <= JSR1;
|
state <= JSR1;
|
end
|
end
|
else if (func==`CROR) begin
|
|
state <= IFETCH;
|
|
case(ir[15:13])
|
|
3'd0: cr0[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
|
|
3'd1: cr1[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
|
|
3'd2: cr2[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
|
|
3'd3: cr3[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
|
|
3'd4: cr4[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
|
|
3'd5: cr5[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
|
|
3'd6: cr6[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
|
|
3'd7: cr7[ir[12:11]] <= GetCrBit(ir[25:21])| GetCrBit(ir[20:16]);
|
|
endcase
|
|
end
|
|
else if (func==`CRAND) begin
|
|
state <= IFETCH;
|
|
case(ir[15:13])
|
|
3'd0: cr0[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
|
|
3'd1: cr1[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
|
|
3'd2: cr2[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
|
|
3'd3: cr3[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
|
|
3'd4: cr4[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
|
|
3'd5: cr5[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
|
|
3'd6: cr6[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
|
|
3'd7: cr7[ir[12:11]] <= GetCrBit(ir[25:21])& GetCrBit(ir[20:16]);
|
|
endcase
|
|
end
|
|
else if (func==`CRXOR) begin
|
|
state <= IFETCH;
|
|
case(ir[15:13])
|
|
3'd0: cr0[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
|
|
3'd1: cr1[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
|
|
3'd2: cr2[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
|
|
3'd3: cr3[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
|
|
3'd4: cr4[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
|
|
3'd5: cr5[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
|
|
3'd6: cr6[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
|
|
3'd7: cr7[ir[12:11]] <= GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]);
|
|
endcase
|
|
end
|
|
else if (func==`CRNOR) begin
|
|
state <= IFETCH;
|
|
case(ir[15:13])
|
|
3'd0: cr0[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
|
|
3'd1: cr1[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
|
|
3'd2: cr2[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
|
|
3'd3: cr3[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
|
|
3'd4: cr4[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
|
|
3'd5: cr5[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
|
|
3'd6: cr6[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
|
|
3'd7: cr7[ir[12:11]] <= ~(GetCrBit(ir[25:21])| GetCrBit(ir[20:16]));
|
|
endcase
|
|
end
|
|
else if (func==`CRNAND) begin
|
|
state <= IFETCH;
|
|
case(ir[15:13])
|
|
3'd0: cr0[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
|
|
3'd1: cr1[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
|
|
3'd2: cr2[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
|
|
3'd3: cr3[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
|
|
3'd4: cr4[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
|
|
3'd5: cr5[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
|
|
3'd6: cr6[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
|
|
3'd7: cr7[ir[12:11]] <= ~(GetCrBit(ir[25:21])& GetCrBit(ir[20:16]));
|
|
endcase
|
|
end
|
|
else if (func==`CRXNOR) begin
|
|
state <= IFETCH;
|
|
case(ir[15:13])
|
|
3'd0: cr0[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
|
|
3'd1: cr1[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
|
|
3'd2: cr2[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
|
|
3'd3: cr3[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
|
|
3'd4: cr4[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
|
|
3'd5: cr5[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
|
|
3'd6: cr6[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
|
|
3'd7: cr7[ir[12:11]] <= ~(GetCrBit(ir[25:21])^ GetCrBit(ir[20:16]));
|
|
endcase
|
|
end
|
|
case(func)
|
case(func)
|
`LWX: begin ea <= a + b; mopcode <= `LW; state <= MEMORY1; end
|
`LWX: begin ea <= a + b; mopcode <= `LW; state <= MEMORY1; end
|
`LHX: begin ea <= a + b; mopcode <= `LH; state <= MEMORY1; end
|
`LHX: begin ea <= a + b; mopcode <= `LH; state <= MEMORY1; end
|
`LHUX: begin ea <= a + b; mopcode <= `LHU; state <= MEMORY1; end
|
`LHUX: begin ea <= a + b; mopcode <= `LHU; state <= MEMORY1; end
|
`LBX: begin ea <= a + b; mopcode <= `LB; state <= MEMORY1; end
|
`LBX: begin ea <= a + b; mopcode <= `LB; state <= MEMORY1; end
|
`LBUX: begin ea <= a + b; mopcode <= `LBU; state <= MEMORY1; end
|
`LBUX: begin ea <= a + b; mopcode <= `LBU; state <= MEMORY1; end
|
`SBX: begin ea <= a + b; mopcode <= `SB; b <= c; state <= MEMORY1; end
|
`SBX: begin ea <= a + b; mopcode <= `SB; b <= c; state <= MEMORY1; end
|
`SHX: begin ea <= a + b; mopcode <= `SH; b <= c; state <= MEMORY1; end
|
`SHX: begin ea <= a + b; mopcode <= `SH; b <= c; state <= MEMORY1; end
|
`SWX: begin ea <= a + b; mopcode <= `SW; b <= c; state <= MEMORY1; end
|
`SWX: begin ea <= a + b; mopcode <= `SW; b <= c; state <= MEMORY1; end
|
|
|
|
`MULU: state <= MULTDIV1;
|
|
`MULS: state <= MULTDIV1;
|
|
`MULUH: state <= MULTDIV1;
|
|
`MULSH: state <= MULTDIV1;
|
|
`DIVU: state <= MULTDIV1;
|
|
`DIVS: state <= MULTDIV1;
|
|
`MODU: state <= MULTDIV1;
|
|
`MODS: state <= MULTDIV1;
|
endcase
|
endcase
|
end
|
end
|
`SETcc:
|
`SETcc:
|
begin
|
begin
|
case(cond)
|
case(cond)
|
| Line 269... |
Line 187... |
`SUBI: res <= a - imm;
|
`SUBI: res <= a - imm;
|
`CMPI: res <= a - imm;
|
`CMPI: res <= a - imm;
|
`ANDI: res <= a & imm;
|
`ANDI: res <= a & imm;
|
`ORI: res <= a | imm;
|
`ORI: res <= a | imm;
|
`EORI: res <= a ^ imm;
|
`EORI: res <= a ^ imm;
|
`CRxx:
|
/*
|
case(ir[20:16])
|
case(ir[20:16])
|
`ORI_CCR:
|
`ORI_CCR:
|
begin
|
begin
|
state <= IFETCH;
|
state <= IFETCH;
|
cr0 <= cr0 | imm[3:0];
|
cr0 <= cr0 | imm[3:0];
|
cr1 <= cr1 | imm[7:4];
|
cr1 <= cr1 | imm[7:4];
|
cr2 <= cr2 | imm[11:8];
|
cr2 <= cr2 | imm[11:8];
|
cr3 <= cr3 | imm[15:12];
|
cr3 <= cr3 | imm[15:12];
|
cr4 <= cr4 | imm[19:16];
|
cr4 <= cr4 | imm[19:16];
|
cr5 <= cr5 | imm[23:20];
|
cr5 <= cr5 | imm[23:20];
|
cr6 <= cr6 | imm[27:24];
|
cr6 <= cr6 | imm[27:24];
|
cr7 <= cr7 | imm[31:28];
|
cr7 <= cr7 | imm[31:28];
|
end
|
end
|
`ANDI_CCR:
|
`ANDI_CCR:
|
begin
|
begin
|
state <= IFETCH;
|
state <= IFETCH;
|
cr0 <= cr0 & imm[3:0];
|
cr0 <= cr0 & imm[3:0];
|
cr1 <= cr1 & imm[7:4];
|
cr1 <= cr1 & imm[7:4];
|
cr2 <= cr2 & imm[11:8];
|
cr2 <= cr2 & imm[11:8];
|
cr3 <= cr3 & imm[15:12];
|
cr3 <= cr3 & imm[15:12];
|
cr4 <= cr4 & imm[19:16];
|
cr4 <= cr4 & imm[19:16];
|
cr5 <= cr5 & imm[23:20];
|
cr5 <= cr5 & imm[23:20];
|
cr6 <= cr6 & imm[27:24];
|
cr6 <= cr6 & imm[27:24];
|
cr7 <= cr7 & imm[31:28];
|
cr7 <= cr7 & imm[31:28];
|
end
|
end
|
`EORI_CCR:
|
`EORI_CCR:
|
begin
|
begin
|
state <= IFETCH;
|
state <= IFETCH;
|
cr0 <= cr0 ^ imm[3:0];
|
cr0 <= cr0 ^ imm[3:0];
|
cr1 <= cr1 ^ imm[7:4];
|
cr1 <= cr1 ^ imm[7:4];
|
cr2 <= cr2 ^ imm[11:8];
|
cr2 <= cr2 ^ imm[11:8];
|
cr3 <= cr3 ^ imm[15:12];
|
cr3 <= cr3 ^ imm[15:12];
|
cr4 <= cr4 ^ imm[19:16];
|
cr4 <= cr4 ^ imm[19:16];
|
cr5 <= cr5 ^ imm[23:20];
|
cr5 <= cr5 ^ imm[23:20];
|
cr6 <= cr6 ^ imm[27:24];
|
cr6 <= cr6 ^ imm[27:24];
|
cr7 <= cr7 ^ imm[31:28];
|
cr7 <= cr7 ^ imm[31:28];
|
end
|
end
|
endcase
|
endcase
|
|
*/
|
`LINK: state <= LINK;
|
`LINK: state <= LINK;
|
|
`MULUI: state <= MULTDIV1;
|
|
`MULSI: state <= MULTDIV1;
|
|
`DIVUI: state <= MULTDIV1;
|
|
`DIVSI: state <= MULTDIV1;
|
default: res <= 32'd0;
|
default: res <= 32'd0;
|
endcase
|
endcase
|
case(opcode)
|
case(opcode)
|
`TAS: begin ea <= a + imm; mopcode <= opcode; state <= TAS; end
|
`TAS: begin ea <= a + imm; mopcode <= opcode; state <= TAS; end
|
`LW: begin ea <= a + imm; mopcode <= opcode; state <= MEMORY1; end
|
`LW: begin ea <= a + imm; mopcode <= opcode; state <= MEMORY1; end
|
