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use work.light52_pkg.all;
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use work.light52_pkg.all;
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use work.light52_ucode_pkg.all;
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use work.light52_ucode_pkg.all;
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entity light52_cpu is
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entity light52_cpu is
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generic (
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generic (
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-- Do not map unused BRAM onto XRAM space.
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USE_BRAM_FOR_XRAM : boolean := false;
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USE_BRAM_FOR_XRAM : boolean := false;
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-- Implement DA and XCHD instructions by default.
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IMPLEMENT_BCD_INSTRUCTIONS : boolean := false;
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IMPLEMENT_BCD_INSTRUCTIONS : boolean := false;
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-- Use a combinational (dedicated) multiplier by default.
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SEQUENTIAL_MULTIPLIER : boolean := false
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SEQUENTIAL_MULTIPLIER : boolean := false
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);
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);
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port(
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port(
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clk : in std_logic;
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clk : in std_logic;
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reset : in std_logic;
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reset : in std_logic;
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| Line 226... |
Line 229... |
-- Present state register and Next state
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-- Present state register and Next state
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signal ps, ns : t_cpu_state;
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signal ps, ns : t_cpu_state;
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---- Interrupt handling --------------------------------------------------------
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---- Interrupt handling --------------------------------------------------------
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-- IRQ inputs ANDed to IE mask bits
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-- IRQ inputs ANDed to IE mask bits.
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signal irq_masked_inputs : std_logic_vector(4 downto 0);
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signal irq_masked_inputs : std_logic_vector(4 downto 0);
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-- IRQ inputs ANDed to IE mask bits ANDed to IP mask bits.
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signal irq_masked_inputs_hp : std_logic_vector(4 downto 0);
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-- Level of highest-level active IRQ input. 0 is highest, 4 lowest, 7 is none.
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-- Level of highest-level active IRQ input. 0 is highest, 4 lowest, 7 is none.
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signal irq_level_inputs : unsigned(2 downto 0);
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signal irq_level_inputs : unsigned(2 downto 0);
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-- Level of IRQ being serviced. 7 if none. Set by IRQ, reset to 7 by RETI.
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signal irq_level_current : unsigned(2 downto 0);
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-- Low 6 bits of IRQ service address.
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-- Low 6 bits of IRQ service address.
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signal irq_vector : unsigned(5 downto 0);
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signal irq_vector : unsigned(5 downto 0);
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signal irq_active : std_logic; -- IRQ pending service
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signal irq_active : std_logic; -- IRQ pending service
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signal load_ie : std_logic; -- IE register load enable
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signal load_ie : std_logic; -- IE register load enable
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signal irq_restore_level : std_logic; -- Restore irq_level_current to 7 (RETI)
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signal load_ip : std_logic; -- IP register load enable
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-- Restore irq priority level (as per RETI execution).
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signal irq_restore_level : std_logic;
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-- High wwhen the active IRQ is allowed by the priority rules.
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signal irq_active_allowed : std_logic;
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-- High when serving a LOw Priority interrupt.
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signal irq_serving_lop : std_logic;
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-- High when serving a HIgh Priority interrupt.
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signal irq_serving_hip : std_logic;
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-- High when the active interrupt line is a HIgh Priority interrupt.
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signal irq_active_hip : std_logic;
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---- CPU programmer's model registers ------------------------------------------
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---- CPU programmer's model registers ------------------------------------------
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signal PC_reg : t_address; -- PC
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signal PC_reg : t_address; -- PC
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signal pc_incremented : t_address; -- PC + 1 | PC, controlled by...
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signal pc_incremented : t_address; -- PC + 1 | PC, controlled by...
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Line 263... |
signal PSW_reg : unsigned(7 downto 1); -- PSW excluding P flag
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signal PSW_reg : unsigned(7 downto 1); -- PSW excluding P flag
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signal PSW : t_byte; -- PSW, full (P is combinational)
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signal PSW : t_byte; -- PSW, full (P is combinational)
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signal SP_reg : t_byte; -- SP
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signal SP_reg : t_byte; -- SP
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signal SP_next : t_byte; -- Next value for SP
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signal SP_next : t_byte; -- Next value for SP
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signal IE_reg : t_byte; -- IE
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signal IE_reg : t_byte; -- IE
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signal IP_reg : t_byte; -- IP
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signal alu_p : std_logic; -- P flag (from ALU)
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signal alu_p : std_logic; -- P flag (from ALU)
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signal DPTR_reg : t_address; -- DPTR
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signal DPTR_reg : t_address; -- DPTR
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signal next_pc : t_address; -- Next value for PC
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signal next_pc : t_address; -- Next value for PC
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Line 910... |
end process cpu_state_machine_transitions;
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end process cpu_state_machine_transitions;
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--## 2.- Interrupt handling ####################################################
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--## 2.- Interrupt handling ####################################################
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-- IP SFR is implemented as a regular SFR as per the MC51 architecture.
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load_ip <= '1' when sfr_addr_internal=SFR_ADDR_IP and sfr_we_internal='1'
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else '0';
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IP_register:
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process(clk)
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begin
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if clk'event and clk='1' then
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if reset='1' then
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IP_reg <= (others => '0');
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else
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if load_ip='1' then
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IP_reg <= alu_result;
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end if;
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end if;
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end if;
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end process IP_register;
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-- IE SFR is implemented as a regular SFR as per the MC51 architecture.
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load_ie <= '1' when sfr_addr_internal=SFR_ADDR_IE and sfr_we_internal='1'
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load_ie <= '1' when sfr_addr_internal=SFR_ADDR_IE and sfr_we_internal='1'
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else '0';
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else '0';
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IE_register:
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IE_register:
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process(clk)
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process(clk)
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Line 954... |
-- if its level is below this. Remember 0 is top, 4 is bottom and 7 is idle.
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-- if its level is below this. Remember 0 is top, 4 is bottom and 7 is idle.
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irq_restore_level <= '1' when ps=ret_0 and alu_fn_reg(0)='1' else '0';
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irq_restore_level <= '1' when ps=ret_0 and alu_fn_reg(0)='1' else '0';
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-- Mask the irq inputs with IE register bits...
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-- Mask the irq inputs with IE register bits...
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irq_masked_inputs <= irq_source and std_logic_vector(IE_reg(4 downto 0));
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irq_masked_inputs <= irq_source and std_logic_vector(IE_reg(4 downto 0));
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-- ...separate the highpriority interrupt inputs by masking with IP register...
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irq_masked_inputs_hp <= irq_masked_inputs and std_logic_vector(IP_reg(4 downto 0));
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-- ...and encode the highest priority active input
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-- ...and encode the highest priority active input
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irq_level_inputs <=
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irq_level_inputs <=
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"000" when irq_masked_inputs_hp(0)='1' else
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"001" when irq_masked_inputs_hp(1)='1' else
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"010" when irq_masked_inputs_hp(2)='1' else
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"011" when irq_masked_inputs_hp(3)='1' else
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"100" when irq_masked_inputs_hp(4)='1' else
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"000" when irq_masked_inputs(0)='1' else
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"000" when irq_masked_inputs(0)='1' else
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"001" when irq_masked_inputs(1)='1' else
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"001" when irq_masked_inputs(1)='1' else
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"010" when irq_masked_inputs(2)='1' else
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"010" when irq_masked_inputs(2)='1' else
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"011" when irq_masked_inputs(3)='1' else
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"011" when irq_masked_inputs(3)='1' else
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"100" when irq_masked_inputs(4)='1' else
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"100" when irq_masked_inputs(4)='1' else
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"111";
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"111";
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irq_active_hip <= '1' when irq_masked_inputs_hp/="00000" else '0';
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-- An active, enabled interrupt will be serviced only if...
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irq_active_allowed <= '1' when
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-- ...other high-priority interrupt is NOT being serviced...
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irq_serving_hip='0' and
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-- ...and either the incoming interrupt is high-priority...
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(irq_active_hip='1' or
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-- -- ...or no interrupt is being serviced at all;
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(irq_active_hip='0' and irq_serving_lop='0'))
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-- otherwise the interrupt is not allowed to proceed.
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else '0';
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-- We have a pending irq if interrupts are enabled...
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-- We have a pending irq if interrupts are enabled...
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irq_active <= '1' when IE_reg(7)='1' and
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irq_active <= '1' when IE_reg(7)='1' and
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-- ...and the active irq has higher priority than any
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-- ...and some interrupt source is active...
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-- ongoing irq routine.
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irq_level_inputs/="111" and
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(irq_level_inputs < irq_level_current)
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-- ...and the active interrupt is allowed by the priority
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-- rules...
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irq_active_allowed='1'
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-- ...otherwise the interrupt is ignored.
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else '0';
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else '0';
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irq_registered_priority_encoder:
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irq_registered_priority_encoder:
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process(clk)
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process(clk)
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begin
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begin
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if clk'event and clk='1' then
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if clk'event and clk='1' then
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if reset='1' or irq_restore_level='1' then
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if reset='1' then
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-- After reset, irq level is 7, which means all irqs are accepted.
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-- After reset, no interrupt of either priority level is being
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-- Note that valid levels are 0 to 4 and the lower the number,
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-- serviced.
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-- the higher the priority.
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irq_serving_hip <= '0';
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-- The level is restored to 7 by the RETI instruction too.
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irq_serving_lop <= '0';
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irq_level_current <= "111";
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elsif irq_restore_level='1' then
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-- RETI executed: if high-priority level was active...
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if irq_serving_hip='1' then
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-- ...disable it, reverting to the previous priority level...
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irq_serving_hip <= '0';
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else
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-- otherwise disable the low priority level.
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irq_serving_lop <= '0';
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end if;
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else
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else
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-- Evaluate and register the interrupt priority in the same state
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-- Evaluate and register the interrupt priority in the same state
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-- the irq is to be acknowledged.
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-- the irq is to be acknowledged.
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if ps=fetch_1 and irq_active='1' then
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if ps=fetch_1 and irq_active='1' then
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irq_level_current <= irq_level_inputs;
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irq_serving_hip <= irq_active_hip;
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irq_serving_lop <= irq_serving_lop or (not irq_active_hip);
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-- This irq vector is going to be used in state irq_2.
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irq_vector <= irq_level_inputs & "011";
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end if;
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end if;
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end if;
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end if;
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end if;
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end if;
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end process irq_registered_priority_encoder;
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end process irq_registered_priority_encoder;
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-- This irq vector is going to be used in state irq_2.
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irq_vector <= irq_level_current & "011";
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--## 3.- Combined register bank & decoding table ###############################
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--## 3.- Combined register bank & decoding table ###############################
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-- No support yet for XRAM on this RAM block
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-- No support yet for XRAM on this RAM block
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Line 1683... |
A_reg when SFR_ADDR_ACC,
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A_reg when SFR_ADDR_ACC,
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B_reg when SFR_ADDR_B,
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B_reg when SFR_ADDR_B,
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DPTR_reg(15 downto 8) when SFR_ADDR_DPH,
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DPTR_reg(15 downto 8) when SFR_ADDR_DPH,
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DPTR_reg( 7 downto 0) when SFR_ADDR_DPL,
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DPTR_reg( 7 downto 0) when SFR_ADDR_DPL,
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IE_reg when SFR_ADDR_IE,
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IE_reg when SFR_ADDR_IE,
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IP_reg when SFR_ADDR_IP,
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unsigned(sfr_rd) when others;
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unsigned(sfr_rd) when others;
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-- Registering the SFR read mux gives the SFR block the same timing behavior as
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-- Registering the SFR read mux gives the SFR block the same timing behavior as
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-- the IRAM block, and improves clock rate a lot.
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-- the IRAM block, and improves clock rate a lot.
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SFR_mux_register:
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SFR_mux_register:
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