| Line 3... |
Line 3... |
use ieee.std_logic_unsigned.all;
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use ieee.std_logic_unsigned.all;
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|
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entity madi_receiver is
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entity madi_receiver is
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port(
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port(
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clk_125_in : in std_logic;
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clk_125_in : in std_logic;
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madi_in : in std_logic;
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madi_clk_in : in std_logic;
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madi_data_valid : in std_logic;
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madi_symbol_in : in std_logic_vector(4 downto 0);
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|
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madi_write : out std_logic;
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madi_write : out std_logic;
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madi_wordclock : out std_logic;
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madi_wordclock : out std_logic;
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madi_channel : out std_logic_vector(5 downto 0) := (others => '0');
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madi_channel : out std_logic_vector(5 downto 0) := (others => '0');
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madi_data : out std_logic_vector(23 downto 0) := (others => '0')
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madi_data : out std_logic_vector(23 downto 0) := (others => '0')
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| Line 15... |
Line 17... |
end madi_receiver;
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end madi_receiver;
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architecture behavioral of madi_receiver is
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architecture behavioral of madi_receiver is
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type nibble_buffer is array(7 downto 0) of std_logic_vector(3 downto 0);
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type nibble_buffer is array(7 downto 0) of std_logic_vector(3 downto 0);
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|
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signal madi_nrzi_shift : std_logic_vector(1 downto 0);
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signal madi_input_shift : std_logic_vector(14 downto 0) := (others => '0');
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signal madi_nrzi_data : std_logic;
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signal madi_clk_shift : std_logic_vector(1 downto 0) := (others => '0');
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signal madi_sync_shift : std_logic_vector(9 downto 0);
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signal madi_sync_detect : std_logic := '0';
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signal madi_sync_count : std_logic_vector(2 downto 0);
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signal madi_aligned : std_logic := '0';
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signal madi_sync_clk : std_logic;
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signal madi_symbol : std_logic_vector(4 downto 0) := (others => '0');
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signal madi_symbol : std_logic_vector(4 downto 0);
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signal madi_symbol_count : std_logic_vector(2 downto 0) := (others => '0');
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signal madi_nibble_clk : std_logic;
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signal madi_sync_count : std_logic_vector(8 downto 0) := (others => '0');
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signal madi_nibble : std_logic_vector(3 downto 0);
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signal madi_nibble_clk : std_logic := '0';
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signal madi_nibble_cnt : std_logic_vector(2 downto 0);
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signal madi_nibble : std_logic_vector(3 downto 0) := (others => '0');
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signal madi_nibble_cnt : std_logic_vector(2 downto 0) := (others => '0');
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signal madi_nibble_buffer : nibble_buffer;
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signal madi_nibble_buffer : nibble_buffer;
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signal madi_nibble_rst : std_logic;
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signal madi_nibble_rst : std_logic := '0';
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signal madi_channel_cnt : std_logic_vector(5 downto 0) := (others => '0');
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signal madi_channel_cnt : std_logic_vector(5 downto 0) := (others => '0');
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signal madi_channel_rst : std_logic := '0';
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signal madi_channel_rst : std_logic := '0';
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signal madi_write_buffer : std_logic;
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signal madi_write_buffer : std_logic := '0';
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signal madi_wordclk_shift : std_logic_vector(1 downto 0);
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signal madi_wordclk_shift : std_logic_vector(1 downto 0);
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signal madi_wordclk_current : std_logic_vector(11 downto 0) := (others => '0');
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signal madi_wordclk_reference : std_logic_vector(24 downto 0) := (others => '0');
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signal madi_wordclk_count : std_logic_vector(11 downto 0) := (others => '0');
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signal madi_wordclk_count : std_logic_vector(11 downto 0) := (others => '0');
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signal madi_wordclk_max : std_logic_vector(11 downto 0) := (others => '0');
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signal madi_wordclk_wait : std_logic_vector(30 downto 0) := (others => '0');
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begin
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begin
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madi_nrzi_in : process (clk_125_in)
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madi_shift_clk : process (clk_125_in)
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begin
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begin
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if clk_125_in'event and clk_125_in = '1' then
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if clk_125_in'event and clk_125_in = '1' then
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madi_nrzi_shift <= madi_nrzi_shift(0) & madi_in;
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madi_clk_shift <= madi_clk_shift(0) & madi_clk_in;
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if madi_nrzi_shift = "01" or madi_nrzi_shift = "10" then
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end if;
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madi_nrzi_data <= '1';
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end process madi_shift_clk;
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madi_shift_input : process (clk_125_in)
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begin
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if clk_125_in'event and clk_125_in = '1' then
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if madi_clk_shift = "01" then
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madi_input_shift <= madi_input_shift(13 downto 4) & madi_symbol_in;
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else
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else
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madi_nrzi_data <= '0';
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madi_input_shift <= madi_input_shift(13 downto 0) & '0';
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end if;
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end if;
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end if;
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end if;
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end process madi_nrzi_in;
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end process madi_shift_input;
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madi_sync : process (clk_125_in)
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madi_detect_sync : process (clk_125_in)
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begin
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begin
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if clk_125_in'event and clk_125_in = '1' then
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if clk_125_in'event and clk_125_in = '1' then
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madi_sync_shift <= madi_sync_shift(madi_sync_shift'left-1 downto 0) & madi_nrzi_data;
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if madi_symbol_count = 4 then
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madi_sync_count <= madi_sync_count + 1;
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madi_symbol_count <= (others => '0');
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if madi_sync_shift = "1100010001" then -- JK sync symbols detected
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if madi_aligned = '1' then
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madi_sync_count <= (others => '0');
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madi_symbol <= madi_input_shift(9 downto 5);
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end if;
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end if;
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if madi_sync_count = 4 then
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madi_sync_clk <= '1';
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madi_symbol <= madi_sync_shift(4 downto 0);
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madi_sync_count <= (others => '0');
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else
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else
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madi_sync_clk <= '0';
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madi_symbol_count <= madi_symbol_count + 1;
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if madi_input_shift(14 downto 5) = "1100010001" then -- JK sync Symbols detected?
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madi_symbol_count <= (others => '0');
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madi_sync_detect <= '1';
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madi_aligned <= '1';
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else
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madi_sync_detect <= '0';
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end if;
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end if;
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end if;
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end if;
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end if;
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end process madi_sync;
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end process madi_detect_sync;
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madi_decode : process (clk_125_in)
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madi_count_symbol : process (clk_125_in)
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begin
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begin
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if clk_125_in'event and clk_125_in = '1' then
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if clk_125_in'event and clk_125_in = '1' then
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if madi_sync_clk = '1' then
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if madi_sync_detect = '1' then
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madi_sync_count <= madi_sync_count + 1;
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end if;
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end if;
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end process madi_count_symbol;
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madi_decode : process (madi_clk_in)
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begin
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if madi_clk_in'event and madi_clk_in = '1' then
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case madi_symbol is
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case madi_symbol is
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when "11110" =>
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when "11110" =>
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madi_nibble <= "0000";
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madi_nibble <= "0000";
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madi_nibble_clk <= '1';
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madi_nibble_clk <= '1';
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madi_nibble_rst <= '0';
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madi_nibble_rst <= '0';
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| Line 127... |
Line 147... |
madi_nibble_rst <= '0';
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madi_nibble_rst <= '0';
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when "11011" =>
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when "11011" =>
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madi_nibble <= "1101";
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madi_nibble <= "1101";
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madi_nibble_clk <= '1';
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madi_nibble_clk <= '1';
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madi_nibble_rst <= '0';
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madi_nibble_rst <= '0';
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when "11101" =>
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when "11100" =>
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madi_nibble <= "1110";
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madi_nibble <= "1110";
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madi_nibble_clk <= '1';
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madi_nibble_clk <= '1';
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madi_nibble_rst <= '0';
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madi_nibble_rst <= '0';
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when "00100" =>
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when "11101" =>
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madi_nibble <= "1111";
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madi_nibble <= "1111";
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madi_nibble_clk <= '1';
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madi_nibble_clk <= '1';
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madi_nibble_rst <= '0';
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madi_nibble_rst <= '0';
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when others =>
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when others =>
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madi_nibble <= "0000";
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madi_nibble <= "0000";
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madi_nibble_clk <= '0';
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madi_nibble_clk <= '0';
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madi_nibble_rst <= '1';
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madi_nibble_rst <= '1';
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end case;
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end case;
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else
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madi_nibble_clk <= '0';
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madi_nibble_rst <= '0';
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end if;
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end if;
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end if;
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end process madi_decode;
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end process madi_decode;
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place_nibble : process (clk_125_in)
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place_nibble : process (madi_clk_in)
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begin
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begin
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if clk_125_in'event and clk_125_in = '1' then
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if madi_clk_in'event and madi_clk_in = '1' then
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if madi_nibble_rst = '1' then
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if madi_nibble_rst = '1' then
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madi_nibble_cnt <= (others => '0');
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madi_nibble_cnt <= (others => '0');
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end if;
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end if;
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if madi_channel_rst = '1' then
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madi_channel_rst <= '0';
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end if;
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if madi_nibble_clk = '1' then
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if madi_nibble_clk = '1' then
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madi_nibble_cnt <= madi_nibble_cnt + 1;
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madi_nibble_cnt <= madi_nibble_cnt + 1;
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case madi_nibble_cnt is
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case madi_nibble_cnt is
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when "000" =>
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when "000" =>
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madi_nibble_buffer(0) <= madi_nibble;
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madi_nibble_buffer(0) <= madi_nibble;
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| Line 174... |
Line 193... |
madi_nibble_buffer(6) <= madi_nibble;
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madi_nibble_buffer(6) <= madi_nibble;
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when "111" =>
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when "111" =>
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madi_nibble_buffer(7) <= madi_nibble;
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madi_nibble_buffer(7) <= madi_nibble;
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when others =>
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when others =>
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end case;
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end case;
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madi_channel_rst <= madi_nibble_buffer(0)(3);
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if madi_nibble(3) = '1' and madi_nibble_cnt = "000" then
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if madi_channel_rst = '1' then
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madi_channel_rst <= '1';
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madi_channel_cnt <= (others => '0');
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madi_channel_cnt <= (others => '0');
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end if;
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end if;
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if madi_nibble_cnt = 7 then
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if madi_nibble_cnt = 7 then
|
madi_data <= madi_nibble_buffer(1) & madi_nibble_buffer(2) & madi_nibble_buffer(3) & madi_nibble_buffer(4) & madi_nibble_buffer(5) & madi_nibble_buffer(6);
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madi_data <= madi_nibble_buffer(1) & madi_nibble_buffer(2) & madi_nibble_buffer(3) & madi_nibble_buffer(4) & madi_nibble_buffer(5) & madi_nibble_buffer(6);
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madi_channel_cnt <= madi_channel_cnt + 1;
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madi_write_buffer <= '1';
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madi_write_buffer <= '1';
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else
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else
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madi_write_buffer <= '0';
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madi_write_buffer <= '0';
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end if;
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end if;
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madi_wordclk_shift <= madi_wordclk_shift(0) & madi_channel_rst;
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if madi_nibble_cnt = 7 then
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madi_write <= madi_write_buffer;
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madi_channel_cnt <= madi_channel_cnt + 1;
|
end if;
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madi_channel <= madi_channel_cnt;
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madi_channel <= madi_channel_cnt;
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end if;
|
end if;
|
|
end if;
|
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madi_write <= madi_write_buffer;
|
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end if;
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end process place_nibble;
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end process place_nibble;
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|
|
generate_madi_wordclk : process (clk_125_in)
|
generate_madi_wordclk : process (clk_125_in)
|
begin
|
begin
|
if clk_125_in'event and clk_125_in = '1' then
|
if clk_125_in'event and clk_125_in = '1' then
|
|
madi_wordclk_shift <= madi_wordclk_shift(0) & madi_channel_rst;
|
if madi_wordclk_shift = "01" then
|
if madi_wordclk_shift = "01" then
|
madi_wordclk_count <= (others => '0');
|
madi_wordclk_count <= (others => '0');
|
|
madi_wordclk_current <= (others => '0');
|
|
if madi_wordclk_current > madi_wordclk_reference(madi_wordclk_reference'left downto madi_wordclk_reference'left-11) then
|
|
madi_wordclk_reference <= madi_wordclk_reference + 1;
|
else
|
else
|
madi_wordclk_count <= madi_wordclk_count + 1;
|
madi_wordclk_reference <= madi_wordclk_reference - 1;
|
end if;
|
end if;
|
if madi_wordclk_count > madi_wordclk_max then
|
|
madi_wordclk_max <= madi_wordclk_count;
|
|
madi_wordclk_wait <= (others => '0');
|
|
else
|
else
|
if madi_wordclk_wait = 2**(madi_wordclk_wait'length-1) then
|
madi_wordclk_count <= madi_wordclk_count + 1;
|
madi_wordclk_wait <= madi_wordclk_wait - 1;
|
madi_wordclk_current <= madi_wordclk_current + 1;
|
end if;
|
|
end if;
|
end if;
|
if madi_wordclk_count < madi_wordclk_max(madi_wordclk_max'left downto 1) then
|
if madi_wordclk_count < madi_wordclk_reference(madi_wordclk_reference'left downto madi_wordclk_reference'left-11) then
|
madi_wordclock <= '1';
|
madi_wordclock <= '1';
|
else
|
else
|
madi_wordclock <= '0';
|
madi_wordclock <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
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| Line 247... |
Line 267... |
bit_count : process (bitclk_in)
|
bit_count : process (bitclk_in)
|
begin
|
begin
|
if bitclk_in'event and bitclk_in='1' then
|
if bitclk_in'event and bitclk_in='1' then
|
wordclk_shift <= wordclk_shift(0) & wordclk_in;
|
wordclk_shift <= wordclk_shift(0) & wordclk_in;
|
bit_counter <= bit_counter + 1;
|
bit_counter <= bit_counter + 1;
|
if wordclk_shift = "01" then
|
|
bit_counter <= (others => '0');
|
|
end if;
|
|
end if;
|
end if;
|
end process bit_count;
|
end process bit_count;
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|
|
proc_adat_buffer : process (bitclk_in, bit_counter, data_in, adat_address)
|
proc_adat_buffer : process (bitclk_in)
|
begin
|
begin
|
if bitclk_in'event and bitclk_in='1' then
|
if bitclk_in'event and bitclk_in='1' then
|
case bit_counter is
|
case bit_counter is
|
when "00000000" =>
|
when "00000000" =>
|
adat_buffer <= data_in(23 downto 20) & '1' & data_in(19 downto 16) & '1' & data_in(15 downto 12) & '1' & data_in(11 downto 8) & '1' & data_in(7 downto 4) & '1' & data_in(3 downto 0) & '1';
|
adat_buffer <= '1' & data_in(0) & data_in(1) & data_in(2) & data_in(3) & '1' & data_in(4) & data_in(5) & data_in(6) & data_in(7) & '1' & data_in(8) & data_in(9) & data_in(10) & data_in(11) & '1' & data_in(12) & data_in(13) & data_in(14) & data_in(15) & '1' & data_in(16) & data_in(17) & data_in(18) & data_in(19) & '1' & data_in(20) & data_in(21) & data_in(22) & data_in(23);
|
when "00000001" =>
|
|
adat_address <= adat_address +1;
|
adat_address <= adat_address +1;
|
when "00011110" =>
|
when "00011110" =>
|
adat_buffer <= data_in(23 downto 20) & '1' & data_in(19 downto 16) & '1' & data_in(15 downto 12) & '1' & data_in(11 downto 8) & '1' & data_in(7 downto 4) & '1' & data_in(3 downto 0) & '1';
|
adat_buffer <= '1' & data_in(0) & data_in(1) & data_in(2) & data_in(3) & '1' & data_in(4) & data_in(5) & data_in(6) & data_in(7) & '1' & data_in(8) & data_in(9) & data_in(10) & data_in(11) & '1' & data_in(12) & data_in(13) & data_in(14) & data_in(15) & '1' & data_in(16) & data_in(17) & data_in(18) & data_in(19) & '1' & data_in(20) & data_in(21) & data_in(22) & data_in(23);
|
when "00011111" =>
|
|
adat_address <= adat_address +1;
|
adat_address <= adat_address +1;
|
when "00111100" =>
|
when "00111100" =>
|
adat_buffer <= data_in(23 downto 20) & '1' & data_in(19 downto 16) & '1' & data_in(15 downto 12) & '1' & data_in(11 downto 8) & '1' & data_in(7 downto 4) & '1' & data_in(3 downto 0) & '1';
|
adat_buffer <= '1' & data_in(0) & data_in(1) & data_in(2) & data_in(3) & '1' & data_in(4) & data_in(5) & data_in(6) & data_in(7) & '1' & data_in(8) & data_in(9) & data_in(10) & data_in(11) & '1' & data_in(12) & data_in(13) & data_in(14) & data_in(15) & '1' & data_in(16) & data_in(17) & data_in(18) & data_in(19) & '1' & data_in(20) & data_in(21) & data_in(22) & data_in(23);
|
when "00111101" =>
|
|
adat_address <= adat_address +1;
|
adat_address <= adat_address +1;
|
when "01011010" =>
|
when "01011010" =>
|
adat_buffer <= data_in(23 downto 20) & '1' & data_in(19 downto 16) & '1' & data_in(15 downto 12) & '1' & data_in(11 downto 8) & '1' & data_in(7 downto 4) & '1' & data_in(3 downto 0) & '1';
|
adat_buffer <= '1' & data_in(0) & data_in(1) & data_in(2) & data_in(3) & '1' & data_in(4) & data_in(5) & data_in(6) & data_in(7) & '1' & data_in(8) & data_in(9) & data_in(10) & data_in(11) & '1' & data_in(12) & data_in(13) & data_in(14) & data_in(15) & '1' & data_in(16) & data_in(17) & data_in(18) & data_in(19) & '1' & data_in(20) & data_in(21) & data_in(22) & data_in(23);
|
when "01011011" =>
|
|
adat_address <= adat_address +1;
|
adat_address <= adat_address +1;
|
when "01111000" =>
|
when "01111000" =>
|
adat_buffer <= data_in(23 downto 20) & '1' & data_in(19 downto 16) & '1' & data_in(15 downto 12) & '1' & data_in(11 downto 8) & '1' & data_in(7 downto 4) & '1' & data_in(3 downto 0) & '1';
|
adat_buffer <= '1' & data_in(0) & data_in(1) & data_in(2) & data_in(3) & '1' & data_in(4) & data_in(5) & data_in(6) & data_in(7) & '1' & data_in(8) & data_in(9) & data_in(10) & data_in(11) & '1' & data_in(12) & data_in(13) & data_in(14) & data_in(15) & '1' & data_in(16) & data_in(17) & data_in(18) & data_in(19) & '1' & data_in(20) & data_in(21) & data_in(22) & data_in(23);
|
when "01111001" =>
|
|
adat_address <= adat_address +1;
|
adat_address <= adat_address +1;
|
when "10010110" =>
|
when "10010110" =>
|
adat_buffer <= data_in(23 downto 20) & '1' & data_in(19 downto 16) & '1' & data_in(15 downto 12) & '1' & data_in(11 downto 8) & '1' & data_in(7 downto 4) & '1' & data_in(3 downto 0) & '1';
|
adat_buffer <= '1' & data_in(0) & data_in(1) & data_in(2) & data_in(3) & '1' & data_in(4) & data_in(5) & data_in(6) & data_in(7) & '1' & data_in(8) & data_in(9) & data_in(10) & data_in(11) & '1' & data_in(12) & data_in(13) & data_in(14) & data_in(15) & '1' & data_in(16) & data_in(17) & data_in(18) & data_in(19) & '1' & data_in(20) & data_in(21) & data_in(22) & data_in(23);
|
when "10010111" =>
|
|
adat_address <= adat_address +1;
|
adat_address <= adat_address +1;
|
when "10110100" =>
|
when "10110100" =>
|
adat_buffer <= data_in(23 downto 20) & '1' & data_in(19 downto 16) & '1' & data_in(15 downto 12) & '1' & data_in(11 downto 8) & '1' & data_in(7 downto 4) & '1' & data_in(3 downto 0) & '1';
|
adat_buffer <= '1' & data_in(0) & data_in(1) & data_in(2) & data_in(3) & '1' & data_in(4) & data_in(5) & data_in(6) & data_in(7) & '1' & data_in(8) & data_in(9) & data_in(10) & data_in(11) & '1' & data_in(12) & data_in(13) & data_in(14) & data_in(15) & '1' & data_in(16) & data_in(17) & data_in(18) & data_in(19) & '1' & data_in(20) & data_in(21) & data_in(22) & data_in(23);
|
when "10110101" =>
|
|
adat_address <= adat_address +1;
|
adat_address <= adat_address +1;
|
when "11010010" =>
|
when "11010010" =>
|
adat_buffer <= data_in(23 downto 20) & '1' & data_in(19 downto 16) & '1' & data_in(15 downto 12) & '1' & data_in(11 downto 8) & '1' & data_in(7 downto 4) & '1' & data_in(3 downto 0) & '1';
|
adat_buffer <= '1' & data_in(0) & data_in(1) & data_in(2) & data_in(3) & '1' & data_in(4) & data_in(5) & data_in(6) & data_in(7) & '1' & data_in(8) & data_in(9) & data_in(10) & data_in(11) & '1' & data_in(12) & data_in(13) & data_in(14) & data_in(15) & '1' & data_in(16) & data_in(17) & data_in(18) & data_in(19) & '1' & data_in(20) & data_in(21) & data_in(22) & data_in(23);
|
when "11010011" =>
|
|
adat_address <= adat_address +1;
|
|
when "11110000" =>
|
|
adat_buffer <= "0000" & '1' & "0000000000" & '1' & "00000000000000";
|
|
when "11110001" =>
|
|
adat_address <= (others => '0');
|
adat_address <= (others => '0');
|
|
when "11110000" =>
|
|
-- Sync sequence USER Dummy bits (no tx)
|
|
adat_buffer <= '1' & "0000000000" & '1' & "0000" & "00000000000000";
|
when others =>
|
when others =>
|
adat_buffer <= adat_buffer(adat_buffer'left-1 downto 0) & '0';
|
adat_buffer <= adat_buffer(adat_buffer'left-1 downto 0) & '0';
|
end case;
|
end case;
|
end if;
|
end if;
|
end process proc_adat_buffer;
|
end process proc_adat_buffer;
|
| Line 315... |
Line 323... |
address_out <= adat_address;
|
address_out <= adat_address;
|
adat_out <= adat_nrzi;
|
adat_out <= adat_nrzi;
|
|
|
end behavioral;
|
end behavioral;
|
|
|
LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
LIBRARY altera_mf;
|
|
USE altera_mf.all;
|
|
|
|
entity dp_ram is
|
|
port(
|
|
clock : in std_logic;
|
|
data : in std_logic_vector(23 downto 0);
|
|
rdaddress : in std_logic_vector(2 downto 0);
|
|
wraddress : in std_logic_vector(2 downto 0);
|
|
wren : in std_logic := '1';
|
|
q : out std_logic_vector(23 downto 0)
|
|
);
|
|
end dp_ram;
|
|
|
|
architecture syn of dp_ram is
|
|
|
|
SIGNAL sub_wire0 : std_logic_vector(23 downto 0);
|
|
|
|
component altsyncram
|
|
generic (
|
|
address_reg_b : string;
|
|
clock_enable_input_a : string;
|
|
clock_enable_input_b : string;
|
|
clock_enable_output_a : string;
|
|
clock_enable_output_b : string;
|
|
intended_device_family : string;
|
|
lpm_type : string;
|
|
numwords_a : natural;
|
|
numwords_b : natural;
|
|
operation_mode : string;
|
|
outdata_aclr_b : string;
|
|
outdata_reg_b : string;
|
|
power_up_uninitialized : string;
|
|
read_during_write_mode_mixed_ports : string;
|
|
widthad_a : natural;
|
|
widthad_b : natural;
|
|
width_a : natural;
|
|
width_b : natural;
|
|
width_byteena_a : natural
|
|
);
|
|
port(
|
|
wren_a : in std_logic ;
|
|
clock0 : in std_logic ;
|
|
address_a : in std_logic_vector(2 downto 0);
|
|
address_b : in std_logic_vector(2 downto 0);
|
|
q_b : out std_logic_vector(23 downto 0);
|
|
data_a : in std_logic_vector(23 downto 0)
|
|
);
|
|
end component;
|
|
|
|
begin
|
|
q <= sub_wire0(23 downto 0);
|
|
altsyncram_component : altsyncram
|
|
generic map(
|
|
address_reg_b => "CLOCK0",
|
|
clock_enable_input_a => "BYPASS",
|
|
clock_enable_input_b => "BYPASS",
|
|
clock_enable_output_a => "BYPASS",
|
|
clock_enable_output_b => "BYPASS",
|
|
intended_device_family => "Cyclone II",
|
|
lpm_type => "altsyncram",
|
|
numwords_a => 8,
|
|
numwords_b => 8,
|
|
operation_mode => "DUAL_PORT",
|
|
outdata_aclr_b => "NONE",
|
|
outdata_reg_b => "CLOCK0",
|
|
power_up_uninitialized => "FALSE",
|
|
read_during_write_mode_mixed_ports => "OLD_DATA",
|
|
widthad_a => 3,
|
|
widthad_b => 3,
|
|
width_a => 24,
|
|
width_b => 24,
|
|
width_byteena_a => 1
|
|
)
|
|
port map(
|
|
wren_a => wren,
|
|
clock0 => clock,
|
|
address_a => wraddress,
|
|
address_b => rdaddress,
|
|
data_a => data,
|
|
q_b => sub_wire0
|
|
);
|
|
end syn;
|
|
|
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
|
|
entity madi_to_adat is
|
entity madi_to_adat is
|
port(
|
port(
|
|
madi_clk_in : in std_logic;
|
|
madi_data_valid : in std_logic;
|
|
madi_symbol_in : in std_logic_vector(4 downto 0);
|
|
|
clk_125_in : in std_logic;
|
clk_125_in : in std_logic;
|
madi_in : in std_logic;
|
|
|
|
word_clk_in : in std_logic;
|
|
word_clk_out : out std_logic;
|
word_clk_out : out std_logic;
|
bit_clk_in : in std_logic;
|
bit_clk_in : in std_logic;
|
adat_0_out : out std_logic;
|
adat_0_out : out std_logic;
|
adat_1_out : out std_logic;
|
adat_1_out : out std_logic;
|
adat_2_out : out std_logic;
|
adat_2_out : out std_logic;
|
| Line 428... |
Line 352... |
|
|
architecture behavioral of madi_to_adat is
|
architecture behavioral of madi_to_adat is
|
signal madi_channel : std_logic_vector(5 downto 0);
|
signal madi_channel : std_logic_vector(5 downto 0);
|
signal madi_data : std_logic_vector(23 downto 0);
|
signal madi_data : std_logic_vector(23 downto 0);
|
signal madi_write : std_logic;
|
signal madi_write : std_logic;
|
|
signal word_clk : std_logic;
|
|
|
signal madi_write_0 : std_logic;
|
signal madi_write_0 : std_logic;
|
signal madi_write_1 : std_logic;
|
signal madi_write_1 : std_logic;
|
signal madi_write_2 : std_logic;
|
signal madi_write_2 : std_logic;
|
signal madi_write_3 : std_logic;
|
signal madi_write_3 : std_logic;
|
| Line 458... |
Line 383... |
signal adat_data_6 : std_logic_vector(23 downto 0);
|
signal adat_data_6 : std_logic_vector(23 downto 0);
|
signal adat_data_7 : std_logic_vector(23 downto 0);
|
signal adat_data_7 : std_logic_vector(23 downto 0);
|
|
|
component madi_receiver is
|
component madi_receiver is
|
port(
|
port(
|
|
madi_clk_in : in std_logic;
|
clk_125_in : in std_logic;
|
clk_125_in : in std_logic;
|
madi_in : in std_logic;
|
madi_data_valid : in std_logic;
|
|
madi_symbol_in : in std_logic_vector(4 downto 0);
|
|
|
madi_write : out std_logic;
|
madi_write : out std_logic;
|
madi_wordclock : out std_logic;
|
madi_wordclock : out std_logic;
|
madi_channel : out std_logic_vector(5 downto 0);
|
madi_channel : out std_logic_vector(5 downto 0);
|
madi_data : out std_logic_vector(23 downto 0)
|
madi_data : out std_logic_vector(23 downto 0)
|
| Line 492... |
Line 419... |
);
|
);
|
end component dp_ram;
|
end component dp_ram;
|
|
|
begin
|
begin
|
|
|
|
word_clk_out <= word_clk;
|
|
|
madi_receive : madi_receiver
|
madi_receive : madi_receiver
|
port map(
|
port map(
|
|
madi_clk_in => madi_clk_in,
|
clk_125_in => clk_125_in,
|
clk_125_in => clk_125_in,
|
madi_in => madi_in,
|
madi_data_valid => madi_data_valid,
|
|
madi_symbol_in => madi_symbol_in,
|
madi_write => madi_write,
|
madi_write => madi_write,
|
madi_wordclock => word_clk_out,
|
madi_wordclock => word_clk,
|
madi_channel => madi_channel,
|
madi_channel => madi_channel,
|
madi_data => madi_data
|
madi_data => madi_data
|
);
|
);
|
|
|
-- adat channel 0
|
-- adat channel 0
|
|
|
dp_ram_0_write : process (clk_125_in)
|
dp_ram_0_write : process (madi_clk_in)
|
begin
|
begin
|
if clk_125_in'event and clk_125_in='1' then
|
if madi_clk_in'event and madi_clk_in='1' then
|
if madi_channel(5 downto 3) = 0 and madi_write = '1' then
|
if madi_channel(5 downto 3) = 0 and madi_write = '1' then
|
madi_write_0 <= '1';
|
madi_write_0 <= '1';
|
else
|
else
|
madi_write_0 <= '0';
|
madi_write_0 <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process dp_ram_0_write;
|
end process dp_ram_0_write;
|
|
|
dp_ram_0 : dp_ram
|
dp_ram_0 : dp_ram
|
port map(
|
port map(
|
clock => clk_125_in,
|
clock => madi_clk_in,
|
data => madi_data,
|
data => madi_data,
|
rdaddress => adat_addr_0,
|
rdaddress => adat_addr_0,
|
wraddress => madi_channel(2 downto 0),
|
wraddress => madi_channel(2 downto 0),
|
wren => madi_write_0,
|
wren => madi_write_0,
|
q => adat_data_0
|
q => adat_data_0
|
| Line 530... |
Line 461... |
adat_transmitter_0 : adat_transmitter
|
adat_transmitter_0 : adat_transmitter
|
port map(
|
port map(
|
data_in => adat_data_0,
|
data_in => adat_data_0,
|
address_out => adat_addr_0,
|
address_out => adat_addr_0,
|
bitclk_in => bit_clk_in,
|
bitclk_in => bit_clk_in,
|
wordclk_in => word_clk_in,
|
wordclk_in => word_clk,
|
adat_out => adat_0_out
|
adat_out => adat_0_out
|
);
|
);
|
|
|
-- adat channel 1
|
-- adat channel 1
|
|
|
dp_ram_1_write : process (clk_125_in)
|
dp_ram_1_write : process (madi_clk_in)
|
begin
|
begin
|
if clk_125_in'event and clk_125_in='1' then
|
if madi_clk_in'event and madi_clk_in='1' then
|
if madi_channel(5 downto 3) = 1 and madi_write = '1' then
|
if madi_channel(5 downto 3) = 1 and madi_write = '1' then
|
madi_write_1 <= '1';
|
madi_write_1 <= '1';
|
else
|
else
|
madi_write_1 <= '0';
|
madi_write_1 <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process dp_ram_1_write;
|
end process dp_ram_1_write;
|
|
|
dp_ram_1 : dp_ram
|
dp_ram_1 : dp_ram
|
port map(
|
port map(
|
clock => clk_125_in,
|
clock => madi_clk_in,
|
data => madi_data,
|
data => madi_data,
|
rdaddress => adat_addr_1,
|
rdaddress => adat_addr_1,
|
wraddress => madi_channel(2 downto 0),
|
wraddress => madi_channel(2 downto 0),
|
wren => madi_write_1,
|
wren => madi_write_1,
|
q => adat_data_1
|
q => adat_data_1
|
| Line 562... |
Line 493... |
adat_transmitter_1 : adat_transmitter
|
adat_transmitter_1 : adat_transmitter
|
port map(
|
port map(
|
data_in => adat_data_1,
|
data_in => adat_data_1,
|
address_out => adat_addr_1,
|
address_out => adat_addr_1,
|
bitclk_in => bit_clk_in,
|
bitclk_in => bit_clk_in,
|
wordclk_in => word_clk_in,
|
wordclk_in => word_clk,
|
adat_out => adat_1_out
|
adat_out => adat_1_out
|
);
|
);
|
|
|
-- adat channel 2
|
-- adat channel 2
|
|
|
dp_ram_2_write : process (clk_125_in)
|
dp_ram_2_write : process (madi_clk_in)
|
begin
|
begin
|
if clk_125_in'event and clk_125_in='1' then
|
if madi_clk_in'event and madi_clk_in='1' then
|
if madi_channel(5 downto 3) = 2 and madi_write = '1' then
|
if madi_channel(5 downto 3) = 2 and madi_write = '1' then
|
madi_write_2 <= '1';
|
madi_write_2 <= '1';
|
else
|
else
|
madi_write_2 <= '0';
|
madi_write_2 <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process dp_ram_2_write;
|
end process dp_ram_2_write;
|
|
|
dp_ram_2 : dp_ram
|
dp_ram_2 : dp_ram
|
port map(
|
port map(
|
clock => clk_125_in,
|
clock => madi_clk_in,
|
data => madi_data,
|
data => madi_data,
|
rdaddress => adat_addr_2,
|
rdaddress => adat_addr_2,
|
wraddress => madi_channel(2 downto 0),
|
wraddress => madi_channel(2 downto 0),
|
wren => madi_write_2,
|
wren => madi_write_2,
|
q => adat_data_2
|
q => adat_data_2
|
| Line 594... |
Line 525... |
adat_transmitter_2 : adat_transmitter
|
adat_transmitter_2 : adat_transmitter
|
port map(
|
port map(
|
data_in => adat_data_2,
|
data_in => adat_data_2,
|
address_out => adat_addr_2,
|
address_out => adat_addr_2,
|
bitclk_in => bit_clk_in,
|
bitclk_in => bit_clk_in,
|
wordclk_in => word_clk_in,
|
wordclk_in => word_clk,
|
adat_out => adat_2_out
|
adat_out => adat_2_out
|
);
|
);
|
|
|
-- adat channel 3
|
-- adat channel 3
|
|
|
dp_ram_3_write : process (clk_125_in)
|
dp_ram_3_write : process (madi_clk_in)
|
begin
|
begin
|
if clk_125_in'event and clk_125_in='1' then
|
if madi_clk_in'event and madi_clk_in='1' then
|
if madi_channel(5 downto 3) = 3 and madi_write = '1' then
|
if madi_channel(5 downto 3) = 3 and madi_write = '1' then
|
madi_write_3 <= '1';
|
madi_write_3 <= '1';
|
else
|
else
|
madi_write_3 <= '0';
|
madi_write_3 <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process dp_ram_3_write;
|
end process dp_ram_3_write;
|
|
|
dp_ram_3 : dp_ram
|
dp_ram_3 : dp_ram
|
port map(
|
port map(
|
clock => clk_125_in,
|
clock => madi_clk_in,
|
data => madi_data,
|
data => madi_data,
|
rdaddress => adat_addr_3,
|
rdaddress => adat_addr_3,
|
wraddress => madi_channel(2 downto 0),
|
wraddress => madi_channel(2 downto 0),
|
wren => madi_write_3,
|
wren => madi_write_3,
|
q => adat_data_3
|
q => adat_data_3
|
| Line 626... |
Line 557... |
adat_transmitter_3 : adat_transmitter
|
adat_transmitter_3 : adat_transmitter
|
port map(
|
port map(
|
data_in => adat_data_3,
|
data_in => adat_data_3,
|
address_out => adat_addr_3,
|
address_out => adat_addr_3,
|
bitclk_in => bit_clk_in,
|
bitclk_in => bit_clk_in,
|
wordclk_in => word_clk_in,
|
wordclk_in => word_clk,
|
adat_out => adat_3_out
|
adat_out => adat_3_out
|
);
|
);
|
|
|
-- adat channel 4
|
-- adat channel 4
|
|
|
dp_ram_4_write : process (clk_125_in)
|
dp_ram_4_write : process (madi_clk_in)
|
begin
|
begin
|
if clk_125_in'event and clk_125_in='1' then
|
if madi_clk_in'event and madi_clk_in='1' then
|
if madi_channel(5 downto 3) = 4 and madi_write = '1' then
|
if madi_channel(5 downto 3) = 4 and madi_write = '1' then
|
madi_write_4 <= '1';
|
madi_write_4 <= '1';
|
else
|
else
|
madi_write_4 <= '0';
|
madi_write_4 <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process dp_ram_4_write;
|
end process dp_ram_4_write;
|
|
|
dp_ram_4 : dp_ram
|
dp_ram_4 : dp_ram
|
port map(
|
port map(
|
clock => clk_125_in,
|
clock => madi_clk_in,
|
data => madi_data,
|
data => madi_data,
|
rdaddress => adat_addr_4,
|
rdaddress => adat_addr_4,
|
wraddress => madi_channel(2 downto 0),
|
wraddress => madi_channel(2 downto 0),
|
wren => madi_write_4,
|
wren => madi_write_4,
|
q => adat_data_4
|
q => adat_data_4
|
| Line 658... |
Line 589... |
adat_transmitter_4 : adat_transmitter
|
adat_transmitter_4 : adat_transmitter
|
port map(
|
port map(
|
data_in => adat_data_4,
|
data_in => adat_data_4,
|
address_out => adat_addr_4,
|
address_out => adat_addr_4,
|
bitclk_in => bit_clk_in,
|
bitclk_in => bit_clk_in,
|
wordclk_in => word_clk_in,
|
wordclk_in => word_clk,
|
adat_out => adat_4_out
|
adat_out => adat_4_out
|
);
|
);
|
|
|
-- adat channel 5
|
-- adat channel 5
|
|
|
dp_ram_5_write : process (clk_125_in)
|
dp_ram_5_write : process (madi_clk_in)
|
begin
|
begin
|
if clk_125_in'event and clk_125_in='1' then
|
if madi_clk_in'event and madi_clk_in='1' then
|
if madi_channel(5 downto 3) = 5 and madi_write = '1' then
|
if madi_channel(5 downto 3) = 5 and madi_write = '1' then
|
madi_write_5 <= '1';
|
madi_write_5 <= '1';
|
else
|
else
|
madi_write_5 <= '0';
|
madi_write_5 <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process dp_ram_5_write;
|
end process dp_ram_5_write;
|
|
|
dp_ram_5 : dp_ram
|
dp_ram_5 : dp_ram
|
port map(
|
port map(
|
clock => clk_125_in,
|
clock => madi_clk_in,
|
data => madi_data,
|
data => madi_data,
|
rdaddress => adat_addr_5,
|
rdaddress => adat_addr_5,
|
wraddress => madi_channel(2 downto 0),
|
wraddress => madi_channel(2 downto 0),
|
wren => madi_write_5,
|
wren => madi_write_5,
|
q => adat_data_5
|
q => adat_data_5
|
| Line 690... |
Line 621... |
adat_transmitter_5 : adat_transmitter
|
adat_transmitter_5 : adat_transmitter
|
port map(
|
port map(
|
data_in => adat_data_5,
|
data_in => adat_data_5,
|
address_out => adat_addr_5,
|
address_out => adat_addr_5,
|
bitclk_in => bit_clk_in,
|
bitclk_in => bit_clk_in,
|
wordclk_in => word_clk_in,
|
wordclk_in => word_clk,
|
adat_out => adat_5_out
|
adat_out => adat_5_out
|
);
|
);
|
|
|
-- adat channel 6
|
-- adat channel 6
|
|
|
dp_ram_6_write : process (clk_125_in)
|
dp_ram_6_write : process (madi_clk_in)
|
begin
|
begin
|
if clk_125_in'event and clk_125_in='1' then
|
if madi_clk_in'event and madi_clk_in='1' then
|
if madi_channel(5 downto 3) = 6 and madi_write = '1' then
|
if madi_channel(5 downto 3) = 6 and madi_write = '1' then
|
madi_write_6 <= '1';
|
madi_write_6 <= '1';
|
else
|
else
|
madi_write_6 <= '0';
|
madi_write_6 <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process dp_ram_6_write;
|
end process dp_ram_6_write;
|
|
|
dp_ram_6 : dp_ram
|
dp_ram_6 : dp_ram
|
port map(
|
port map(
|
clock => clk_125_in,
|
clock => madi_clk_in,
|
data => madi_data,
|
data => madi_data,
|
rdaddress => adat_addr_6,
|
rdaddress => adat_addr_6,
|
wraddress => madi_channel(2 downto 0),
|
wraddress => madi_channel(2 downto 0),
|
wren => madi_write_6,
|
wren => madi_write_6,
|
q => adat_data_6
|
q => adat_data_6
|
| Line 722... |
Line 653... |
adat_transmitter_6 : adat_transmitter
|
adat_transmitter_6 : adat_transmitter
|
port map(
|
port map(
|
data_in => adat_data_6,
|
data_in => adat_data_6,
|
address_out => adat_addr_6,
|
address_out => adat_addr_6,
|
bitclk_in => bit_clk_in,
|
bitclk_in => bit_clk_in,
|
wordclk_in => word_clk_in,
|
wordclk_in => word_clk,
|
adat_out => adat_6_out
|
adat_out => adat_6_out
|
);
|
);
|
|
|
-- adat channel 7
|
-- adat channel 7
|
|
|
dp_ram_7_write : process (clk_125_in)
|
dp_ram_7_write : process (madi_clk_in)
|
begin
|
begin
|
if clk_125_in'event and clk_125_in='1' then
|
if madi_clk_in'event and madi_clk_in='1' then
|
if madi_channel(5 downto 3) = 7 and madi_write = '1' then
|
if madi_channel(5 downto 3) = 7 and madi_write = '1' then
|
madi_write_7 <= '1';
|
madi_write_7 <= '1';
|
else
|
else
|
madi_write_7 <= '0';
|
madi_write_7 <= '0';
|
end if;
|
end if;
|
end if;
|
end if;
|
end process dp_ram_7_write;
|
end process dp_ram_7_write;
|
|
|
dp_ram_7 : dp_ram
|
dp_ram_7 : dp_ram
|
port map(
|
port map(
|
clock => clk_125_in,
|
clock => madi_clk_in,
|
data => madi_data,
|
data => madi_data,
|
rdaddress => adat_addr_7,
|
rdaddress => adat_addr_7,
|
wraddress => madi_channel(2 downto 0),
|
wraddress => madi_channel(2 downto 0),
|
wren => madi_write_7,
|
wren => madi_write_7,
|
q => adat_data_7
|
q => adat_data_7
|
| Line 754... |
Line 685... |
adat_transmitter_7 : adat_transmitter
|
adat_transmitter_7 : adat_transmitter
|
port map(
|
port map(
|
data_in => adat_data_7,
|
data_in => adat_data_7,
|
address_out => adat_addr_7,
|
address_out => adat_addr_7,
|
bitclk_in => bit_clk_in,
|
bitclk_in => bit_clk_in,
|
wordclk_in => word_clk_in,
|
wordclk_in => word_clk,
|
adat_out => adat_7_out
|
adat_out => adat_7_out
|
);
|
);
|
|
|
end behavioral;
|
end behavioral;
|
No newline at end of file
|
No newline at end of file
|
