| Line 25... |
Line 25... |
WIDTH : integer := 32;
|
WIDTH : integer := 32;
|
SIZE : integer := 11
|
SIZE : integer := 11
|
);
|
);
|
PORT
|
PORT
|
(
|
(
|
dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
|
dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
|
dat_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
|
dat_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
|
adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
|
adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
|
wre_i : IN std_ulogic_vector(3 DOWNTO 0);
|
wre_i : IN std_logic_vector(3 DOWNTO 0);
|
ena_i : IN std_ulogic;
|
ena_i : IN std_logic;
|
clk_i : IN std_ulogic
|
clk_i : IN std_logic
|
);
|
);
|
END sram_4en_init;
|
END sram_4en_init;
|
|
|
ARCHITECTURE arch OF sram_4en_init IS
|
ARCHITECTURE arch OF sram_4en_init IS
|
TYPE ram_type IS array (0 TO 2 ** SIZE - 1) OF std_ulogic_vector(WIDTH - 1 DOWNTO 0);
|
TYPE ram_type IS array (0 TO 2 ** SIZE - 1) OF std_logic_vector(WIDTH - 1 DOWNTO 0);
|
SIGNAL ram : ram_type := (
|
SIGNAL ram : ram_type := (
|
X"B8080050",X"00000000",X"B8080728",X"00000000",X"B8080738",X"00000000",X"00000000",X"00000000",
|
X"B8080050",X"00000000",X"B8080728",X"00000000",X"B8080738",X"00000000",X"00000000",X"00000000",
|
X"B8080730",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
|
X"B8080730",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
|
X"00000000",X"00000000",X"00000000",X"00000000",X"31A01028",X"30400F18",X"B0000000",X"30209038",
|
X"00000000",X"00000000",X"00000000",X"00000000",X"31A01028",X"30400F18",X"B0000000",X"30209038",
|
X"B9F400C0",X"80000000",X"B9F406E8",X"30A30000",X"B8000000",X"E0601028",X"3021FFE4",X"F9E10000",
|
X"B9F400C0",X"80000000",X"B9F406E8",X"30A30000",X"B8000000",X"E0601028",X"3021FFE4",X"F9E10000",
|
| Line 294... |
Line 294... |
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
|
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
|
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
|
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
|
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
|
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",
|
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000");
|
X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000",X"00000000");
|
|
|
SIGNAL di0, di1, di2, di3 : std_ulogic_vector(WIDTH/4 - 1 DOWNTO 0);
|
SIGNAL di0, di1, di2, di3 : std_logic_vector(WIDTH/4 - 1 DOWNTO 0);
|
BEGIN
|
BEGIN
|
process(wre_i, dat_i, adr_i)
|
process(wre_i, dat_i, adr_i)
|
begin
|
begin
|
if wre_i(0) = '1' then
|
if wre_i(0) = '1' then
|
di0 <= dat_i(WIDTH/4 - 1 DOWNTO 0);
|
di0 <= dat_i(WIDTH/4 - 1 DOWNTO 0);
|
