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[/] [mblite/] [trunk/] [hw/] [std/] [dsram.vhd] - Diff between revs 2 and 6
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| Rev 2 |
Rev 6 |
| Line 25... |
Line 25... |
WIDTH : positive := 32;
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WIDTH : positive := 32;
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SIZE : positive := 8
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SIZE : positive := 8
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);
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);
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PORT
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PORT
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(
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(
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dat_o : OUT std_ulogic_vector(WIDTH - 1 DOWNTO 0);
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dat_o : OUT std_logic_vector(WIDTH - 1 DOWNTO 0);
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adr_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
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adr_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
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ena_i : IN std_ulogic;
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ena_i : IN std_logic;
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dat_w_i : IN std_ulogic_vector(WIDTH - 1 DOWNTO 0);
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dat_w_i : IN std_logic_vector(WIDTH - 1 DOWNTO 0);
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adr_w_i : IN std_ulogic_vector(SIZE - 1 DOWNTO 0);
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adr_w_i : IN std_logic_vector(SIZE - 1 DOWNTO 0);
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wre_i : IN std_ulogic;
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wre_i : IN std_logic;
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clk_i : IN std_ulogic
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clk_i : IN std_logic
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);
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);
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END dsram;
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END dsram;
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ARCHITECTURE arch OF dsram IS
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ARCHITECTURE arch OF dsram IS
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TYPE ram_type IS array(2 ** SIZE - 1 DOWNTO 0) OF std_ulogic_vector(WIDTH - 1 DOWNTO 0);
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TYPE ram_type IS array(2 ** SIZE - 1 DOWNTO 0) OF std_logic_vector(WIDTH - 1 DOWNTO 0);
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SIGNAL ram : ram_type;
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SIGNAL ram : ram_type;
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BEGIN
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BEGIN
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PROCESS(clk_i)
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PROCESS(clk_i)
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BEGIN
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BEGIN
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IF rising_edge(clk_i) THEN
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IF rising_edge(clk_i) THEN
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