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`timescale 1ns / 1ps
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`default_nettype none
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////////////////////////////////////////////////////////////////////////
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//
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// 4004 Arithmetic Logic Unit
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//
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// This file is part of the MCS-4 project hosted at OpenCores:
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// http://www.opencores.org/cores/mcs-4/
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//
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// Copyright © 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
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//
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// These materials are provided under the Creative Commons
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// "Attribution-NonCommercial-ShareAlike" Public License. They
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// are NOT "public domain" and are protected by copyright.
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//
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// This work based on materials provided by Intel Corporation and
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// others under the same license. See the file doc/License for
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// details of this license.
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//
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////////////////////////////////////////////////////////////////////////
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module alu(
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input wire sysclk,
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// Inputs from the Timing and I/O board
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input wire a12,
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input wire m12,
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input wire x12,
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input wire poc,
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// Common 4-bit data bus
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inout wire [3:0] data,
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// Outputs to the Instruction Decode board
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output wire acc_0,
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output wire add_0,
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output reg cy_1,
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// Inputs from the Instruction Decode board
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input wire cma,
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input wire write_acc_1,
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input wire write_carry_2,
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input wire read_acc_3,
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input wire add_group_4,
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input wire inc_group_5,
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input wire sub_group_6,
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input wire ior,
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input wire iow,
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input wire ral,
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input wire rar,
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input wire ope_n,
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input wire daa,
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input wire dcl,
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input wire inc_isz,
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input wire kbp,
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input wire o_ib,
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input wire tcs,
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input wire xch,
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input wire n0342,
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input wire x21_clk2,
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input wire x31_clk2,
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input wire com_n,
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// Outputs to external pins
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output wire cmram0,
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output wire cmram1,
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output wire cmram2,
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output wire cmram3,
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output wire cmrom
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);
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reg [3:0] acc;
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reg cy;
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// Decode logic
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wire n0854 = ~(~x12);
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wire n0351 = ~(x21_clk2 | ~dcl);
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wire n0415 = ~(x21_clk2 | ope_n);
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wire add_ib = ~(x31_clk2 | ~inc_isz);
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wire cy_ib = ~(x31_clk2 | ~iow);
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wire acb_ib = ~((x31_clk2 | ~xch) & (x21_clk2 | ~iow));
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wire n0477 = ~((~x31_clk2 & ~ior) | (a12 & ior));
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wire adc_cy = ~(write_carry_2 | n0477);
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wire add_acc = ~(write_acc_1 | n0477);
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wire adsr = ~(x31_clk2 | ~rar);
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wire adsl = ~(x31_clk2 | ~ral);
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wire acc_adac = ~(~cma | n0342);
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wire acc_ada = ~(read_acc_3 | n0342);
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wire cy_ada = ~(add_group_4 | n0342);
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wire cy_adac = ~(sub_group_6 | n0342);
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// Latch the incoming data bus
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reg [3:0] tmp; // It's the name used in simulator!
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always @(posedge sysclk) begin
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if (~n0342)
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tmp <= data;
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if (m12)
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tmp <= 4'b1111;
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end
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// Invert some of the incoming data
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reg n0893, n0891, n0889, n0887; // D3, D2, D1, D0
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always @(posedge sysclk) begin
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if (sub_group_6) begin
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n0887 <= tmp[0];
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n0889 <= ~tmp[1];
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n0891 <= tmp[2];
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n0893 <= ~tmp[3];
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end
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if (~(sub_group_6 | m12)) begin
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n0887 <= ~tmp[0];
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n0889 <= tmp[1];
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n0891 <= ~tmp[2];
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n0893 <= tmp[3];
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end
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end
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// Feedback from Accumulator
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reg n0873, n0872, n0871, n0870;
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always @(posedge sysclk) begin
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if (acc_ada)
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{n0873, n0872, n0871, n0870} <= acc ^ 4'b1010;
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if (acc_adac)
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{n0873, n0872, n0871, n0870} <= acc ^ 4'b0101;
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if (m12)
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{n0873, n0872, n0871, n0870} <= 4'b1010;
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end
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// Carry generator
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wire n0546 = ~(inc_group_5 | n0342);
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reg n0550;
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always @(posedge sysclk) begin
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if (m12) n0550 <= 1'b0;
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if (n0546) n0550 <= 1'b1;
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if (cy_adac) n0550 <= ~cy;
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if (cy_ada) n0550 <= cy;
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end
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wire n0911 = ~(n0550 ? (n0887 | n0870) : (n0887 & n0870));
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wire n0553 = n0911;
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wire n0912 = ~(n0553 ? (n0889 | n0871) : (n0889 & n0871));
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wire n0556 = n0912;
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wire n0913 = ~(n0556 ? (n0891 | n0872) : (n0891 & n0872));
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wire n0559 = n0913;
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wire n0914 = ~(n0559 ? (n0893 | n0873) : (n0893 & n0873));
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wire n0861 = n0914;
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// Adder
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wire n0878 = ~((n0887 & n0550 & n0870) | (n0553 & (n0887 | n0870 | n0550)));
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wire n0875 = ~((n0889 & n0553 & n0871) | (n0556 & (n0889 | n0871 | n0553)));
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wire n0879 = ~((n0891 & n0556 & n0872) | (n0559 & (n0891 | n0872 | n0556)));
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wire n0877 = ~((n0893 & n0559 & n0873) | (n0861 & (n0893 | n0873 | n0559)));
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wire n0846 = ~n0878;
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wire n0847 = n0875;
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wire n0848 = ~n0879;
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wire n0514 = n0877;
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// Shifter / Accumulator and Carry
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reg [3:0] acc_out; // {n0356, n0348, n0347, n0346}
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wire n0803 = ~((acc_out[3] & (acc_out[2] | acc_out[1])) | cy_1);
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wire n0403 = ~(~daa | n0803);
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wire [3:0] acc_in = {n0514, n0848, n0847, n0846};
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always @(posedge sysclk) begin
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if (adsr)
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{acc, cy} <= {cy_1, acc_in};
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if (add_acc)
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acc <= acc_in;
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if (adsl)
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{cy, acc} <= {acc_in, cy_1};
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if (adc_cy)
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cy <= n0861;
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if (n0403 & n0415)
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cy <= 1'b1;
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// Dynamic refresh would occur during M12
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end
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// Accumulator output latch
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always @(posedge sysclk) begin
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if (n0854) begin
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cy_1 <= cy;
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acc_out <= acc;
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end
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end
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assign acc_0 = ~|acc_out;
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assign add_0 = ~|acc_in;
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// Keyboard Process logic
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wire n0378 = ~((daa & n0803) | o_ib);
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wire n0345 = kbp & (acc_out == 4'b1000);
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wire n0354 = kbp & (acc_out == 4'b0100);
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wire n0363 = kbp & (acc_out == 4'b0010);
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wire n0370 = kbp & (acc_out == 4'b0001);
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wire n0377 = (kbp & (acc_out == 4'b0000)) | ~n0378;
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wire n0358 = ~(n0345 | n0354 | n0363 | n0370 | n0377 | n0403);
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wire n0366 = ~( n0354 | n0363 | n0370 | n0377 | tcs );
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wire n0359 = ~(n0345 | n0370 | n0377 | tcs );
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wire n0357 = ~(n0345 | n0363 | n0377 | n0403);
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// Data output mux
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reg [3:0] dout;
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always @(*) begin
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dout = 4'bzzzz;
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if (acb_ib)
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dout = acc_out;
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if (add_ib)
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dout = acc_in;
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if (cy_ib)
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dout = {3'bxxx, cy_1};
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if (n0415)
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dout = {n0358, n0366, n0359, n0357};
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end
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assign data = dout;
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// Generate CMROM / CMRAMn
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// This may get moved to the Timing & I/O board
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// Inputs: {n0355, n0364, n0371}, n0351, poc, com_n
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wire n0355 = ~acc_out[2];
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wire n0364 = ~acc_out[1];
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wire n0371 = ~acc_out[0];
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reg n0749, n0750, n0751;
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always @(posedge sysclk) begin
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if (poc) begin
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n0749 <= 1'b1;
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n0750 <= 1'b1;
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n0751 <= 1'b1;
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end
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else begin
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if (n0351) begin
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n0749 <= n0355;
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n0750 <= n0364;
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n0751 <= n0371;
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end
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end
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end
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assign cmram3 = ~(com_n | n0749);
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assign cmram2 = ~(com_n | n0750);
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assign cmram1 = ~(com_n | n0751);
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assign cmram0 = ~(com_n | ~n0749 | ~n0750 | ~n0751);
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assign cmrom = ~(com_n | poc);
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endmodule
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No newline at end of file
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No newline at end of file
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