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`timescale 1ns / 1ps
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`default_nettype none
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////////////////////////////////////////////////////////////////////////
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//
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// 4004 Instruction Decoder
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//
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// This file is part of the MCS-4 project hosted at OpenCores:
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// http://www.opencores.org/cores/mcs-4/
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//
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// Copyright © 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
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//
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// These materials are provided under the Creative Commons
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// "Attribution-NonCommercial-ShareAlike" Public License. They
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// are NOT "public domain" and are protected by copyright.
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//
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// This work based on materials provided by Intel Corporation and
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// others under the same license. See the file doc/License for
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// details of this license.
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//
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////////////////////////////////////////////////////////////////////////
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module instruction_decode(
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input wire sysclk, // 50 MHz FPGA clock
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// Inputs from the Timing and I/O board
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input wire clk1,
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input wire clk2,
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input wire a22,
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input wire m12,
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input wire m22,
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input wire x12,
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input wire x22,
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input wire x32,
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input wire poc, // Power-On Clear (reset)
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input wire n0432, // Conditioned TEST_PAD
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// Common 4-bit data bus
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inout wire [3:0] data,
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// These drive the Instruction Pointer (IP) board
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output wire jcn_isz, // JCN+ISZ
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output wire jin_fin, // JIN+FIN
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output wire jun_jms, // JUN+JMS
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output wire cn_n, // ~CN
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output wire bbl, // BBL
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output wire jms, // JMS
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// Outputs to both the IP and SP boards
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output wire sc, // SC (Single Cycle)
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output wire dc, // DC (Double Cycle, ~SC)
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// Outputs to the Scratch Pad (SP) board
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output wire n0636, // JIN+FIN
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output wire sc_m22_clk2, // SC&M22&CLK2
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output wire fin_fim_src_jin, // FIN+FIM+SRC+JIN
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output wire inc_isz_add_sub_xch_ld, // INC+ISZ+ADD+SUB+XCH+LD
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output wire inc_isz_xch, // INC+ISZ+XCH
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output wire opa0_n, // ~OPA.0
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// Inputs from the ALU board (condition bits)
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input wire acc_0, // ACC_0
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input wire add_0, // ADD_0
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input wire cy_1, // CY_1
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// Outputs to the Arithmetic Logic Unit (ALU) board
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output wire cma,
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output wire write_acc_1,
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output wire write_carry_2,
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output wire read_acc_3,
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output wire add_group_4,
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output wire inc_group_5,
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output wire sub_group_6,
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output wire ior,
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output wire iow,
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output wire ral,
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output wire rar,
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output wire ope_n,
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output wire daa,
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output wire dcl,
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output wire inc_isz,
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output wire kbp,
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output wire o_ib,
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output wire tcs,
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output wire xch,
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output wire n0342,
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output wire x21_clk2,
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output wire x31_clk2,
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output wire com_n
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);
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wire sc_m12_clk2 = sc & m12 & clk2;
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assign sc_m22_clk2 = sc & m22 & clk2;
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// Latch the first 4 bits of the opcode
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reg [3:0] opr = 4'b0000;
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always @(posedge sysclk) begin
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if (sc_m12_clk2)
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opr <= data;
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end
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// Latch the second 4 bits of the opcode
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reg [3:0] opa = 4'b0000;
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always @(posedge sysclk) begin
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if (sc_m22_clk2)
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opa <= data;
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end
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assign opa0_n = ~opa[0];
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// Full OPR Decoding
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wire nop = (opr == 4'b0000);
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wire jcn = (opr == 4'b0001);
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wire fim_src = (opr == 4'b0010);
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assign jin_fin = (opr == 4'b0011);
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wire jun = (opr == 4'b0100);
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assign jms = (opr == 4'b0101);
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wire inc = (opr == 4'b0110);
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wire isz = (opr == 4'b0111);
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wire add = (opr == 4'b1000);
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wire sub = (opr == 4'b1001);
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wire ld = (opr == 4'b1010);
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assign xch = (opr == 4'b1011);
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assign bbl = (opr == 4'b1100);
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wire ldm = (opr == 4'b1101);
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wire io = (opr == 4'b1110);
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wire ope = (opr == 4'b1111);
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assign ope_n = ~ope;
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assign n0636 = jin_fin;
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assign jcn_isz = jcn | isz;
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assign jun_jms = jun | jms;
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wire ldm_bbl = ldm | bbl;
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assign inc_isz = (inc | isz) & sc;
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assign inc_isz_xch = inc | isz | xch;
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assign inc_isz_add_sub_xch_ld = inc | isz | add | sub | xch | ld;
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assign fin_fim_src_jin = fim_src | jin_fin;
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// OPE: OPA Decoding
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assign o_ib = ope & (opa[3] == 1'b0);
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wire clb = ope & (opa == 4'b0000);
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wire clc = ope & (opa == 4'b0001);
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wire iac = ope & (opa == 4'b0010);
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wire cmc = ope & (opa == 4'b0011);
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assign cma = ope & (opa == 4'b0100);
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assign ral = ope & (opa == 4'b0101);
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assign rar = ope & (opa == 4'b0110);
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wire tcc = ope & (opa == 4'b0111);
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wire dac = ope & (opa == 4'b1000);
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assign tcs = ope & (opa == 4'b1001);
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wire stc = ope & (opa == 4'b1010);
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assign daa = ope & (opa == 4'b1011);
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assign kbp = ope & (opa == 4'b1100);
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assign dcl = ope & (opa == 4'b1101);
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// IO: OPA Decoding
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assign iow = io & (opa[3] == 1'b0);
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assign ior = io & (opa[3] == 1'b1);
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wire adm = io & (opa == 4'b1011);
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wire sbm = io & (opa == 4'b1000);
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wire fin_fim = fin_fim_src_jin & ~opa[0];
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wire src = fim_src & opa[0];
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assign write_acc_1 = ~(kbp | tcs | daa | xch | poc | cma | tcc | dac | iac |
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clb | ior | ld | sub | add | ldm_bbl);
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assign write_carry_2 = ~(tcs | poc | tcc | stc | cmc | dac | iac |
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clc | clb | sbm | adm | sub | add);
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assign read_acc_3 = ~(daa | rar | ral | dac | iac | sbm | adm | sub | add);
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assign add_group_4 = ~(tcs | tcc | adm | add);
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assign inc_group_5 = ~(inc_isz | stc | iac);
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assign sub_group_6 = ~(cmc | sbm | sub | m12);
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// The Condition Flip-Flop
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reg n0397;
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wire n0486 = ~((opa[2] & acc_0) | (opa[1] & cy_1) | (opa[0] & n0432));
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wire n0419 = ~((add_0 | ~isz) & (~jcn | ((n0486 | opa[3]) & (~n0486 | ~opa[3]))));
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wire n0413 = ~((sc & n0419 & x32) | (~x32 & n0397));
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reg n0405;
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always @(posedge sysclk) begin
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if (clk2)
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n0405 <= n0413;
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end
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always @(posedge sysclk) begin
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if (clk1)
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n0397 <= ~n0405;
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end
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assign cn_n = ~n0397;
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// The Single-Cycle Flip-Flop
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reg n0343 = 1'b0;
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wire n0368 = ~((sc & (fin_fim | jcn_isz | jun_jms) & x32) | (n0343 & ~x32));
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reg n0362 = 1'b1;
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always @(posedge sysclk) begin
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if (clk2)
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n0362 <= n0368;
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if (clk1)
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n0343 <= ~n0362;
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end
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assign sc = ~n0343;
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assign dc = ~sc;
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// Generate ~(X21&~CLK2)
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reg n0360;
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always @(posedge sysclk) begin
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if (clk2)
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n0360 <= ~x12;
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end
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wire n0337 = ~(n0360 | clk2);
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assign x21_clk2 = ~n0337;
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// Generate ~(X31&~CLK2)
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reg n0380;
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always @(posedge sysclk) begin
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if (clk2)
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n0380 <= ~x22;
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end
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wire n0375 = ~(n0380 | clk2);
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assign x31_clk2 = ~n0375;
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// Generate ~COM
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wire n0329 = io;
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reg n0414, n0797;
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always @(posedge sysclk) begin
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if (clk2)
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n0414 <= a22;
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else
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n0797 <= n0414;
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end
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reg n0433, n0801;
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always @(posedge sysclk) begin
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if (clk2)
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n0433 <= m12;
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else
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n0801 <= n0433;
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end
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reg n0425, n0805;
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always @(posedge sysclk) begin
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if (clk2)
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n0425 <= x12;
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else
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n0805 <= n0425;
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end
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wire n0782 = ~((n0801 & n0329) | (src & n0805) | n0797);
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assign com_n = n0782;
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// Generate N0342
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wire n0332 = ~(((n0329 | poc) & x22 & clk2) | (~(n0329 | poc) & n0337 & clk1));
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assign n0342 = n0332;
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// Output OPA onto the data bus
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wire opa_ib = (ldm_bbl | jun_jms) & ~x21_clk2;
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assign data = opa_ib ? opa : 4'bzzzz;
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endmodule
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No newline at end of file
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