| Line 5... |
Line 5... |
// 4004 Scratchpad Register Array
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// 4004 Scratchpad Register Array
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//
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//
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// This file is part of the MCS-4 project hosted at OpenCores:
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// This file is part of the MCS-4 project hosted at OpenCores:
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// http://www.opencores.org/cores/mcs-4/
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// http://www.opencores.org/cores/mcs-4/
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//
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//
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// Copyright © 2012, 2020 by Reece Pollack <rrpollack@opencores.org>
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// Copyright © 2012, 2021 by Reece Pollack <rrpollack@opencores.org>
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//
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//
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// These materials are provided under the Creative Commons
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// These materials are provided under the Creative Commons
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// "Attribution-NonCommercial-ShareAlike" Public License. They
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// "Attribution-NonCommercial-ShareAlike" (CC BY-NC-SA) Public License.
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// are NOT "public domain" and are protected by copyright.
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// They are NOT "public domain", and are protected by copyright.
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//
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//
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// This work based on materials provided by Intel Corporation and
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// This work based on materials provided by Intel Corporation and
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// others under the same license. See the file doc/License for
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// others under the same license. See the file doc/License for
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// details of this license.
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// details of this license.
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//
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//
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| Line 55... |
Line 55... |
reg [3:0] din_n;
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reg [3:0] din_n;
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// Refresh counter stuff
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// Refresh counter stuff
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wire [2:0] reg_rfsh; // Row Refresh counter
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wire [2:0] reg_rfsh; // Row Refresh counter
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wire reg_rfsh_step; // SC&A12&CLK2
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wire reg_rfsh_step; // SC&A12&CLK2
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wire n0571;
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wire n0574;
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wire n0600;
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wire n0610;
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assign reg_rfsh_step = sc & a12 & clk2;
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assign reg_rfsh_step = sc & a12 & clk2;
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counter reg_rfsh_0 (
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counter reg_rfsh_0 (
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.sysclk(sysclk),
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.sysclk(sysclk),
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.step_a(clk1),
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.step_a_in(clk1),
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.step_b(reg_rfsh_step),
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.step_b_in(reg_rfsh_step),
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.q(reg_rfsh[0])
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.step_a_out(n0571),
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.step_b_out(n0574),
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.q(reg_rfsh[0]),
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.qn()
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);
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);
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counter reg_rfsh_1 (
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counter reg_rfsh_1 (
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.sysclk(sysclk),
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.sysclk(sysclk),
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.step_a( reg_rfsh[0]),
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.step_a_in(n0571),
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.step_b(~reg_rfsh[0]),
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.step_b_in(n0574),
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.q(reg_rfsh[1])
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.step_a_out(n0600),
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.step_b_out(n0610),
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.q(reg_rfsh[1]),
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.qn()
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);
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);
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counter reg_rfsh_2 (
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counter reg_rfsh_2 (
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.sysclk(sysclk),
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.sysclk(sysclk),
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.step_a( reg_rfsh[1]),
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.step_a_in(n0600),
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.step_b(~reg_rfsh[1]),
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.step_b_in(n0610),
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.q(reg_rfsh[2])
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.step_a_out(),
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.step_b_out(),
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.q(reg_rfsh[2]),
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.qn()
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);
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);
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// Row selection mux
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// Row selection mux
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reg [2:0] row; // {N0646, N0617, N0582}
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reg [2:0] row; // {N0646, N0617, N0582}
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always @(posedge sysclk) begin
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always @(posedge sysclk) begin
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| Line 126... |
Line 139... |
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// Force row 0 if FIN&X12
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// Force row 0 if FIN&X12
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wire fin_x12 = (n0636 & opa0_n) & x12;
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wire fin_x12 = (n0636 & opa0_n) & x12;
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// Manage the row data buffer
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// Manage the row data buffer
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wire [7:0] row_data = dram_array[fin_x12 ? 3'b000 : row];
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always @(posedge sysclk) begin
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always @(posedge sysclk) begin
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if (precharge)
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if (precharge)
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dram_temp <= 8'b0;
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dram_temp <= 8'b0;
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if (row_read)
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if (row_read)
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dram_temp <= dram_array[fin_x12 ? 3'b000 : row];
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dram_temp <= row_data;
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if (wrab0)
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if (wrab0)
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dram_temp[ 7:4] <= ~din_n;
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dram_temp[ 7:4] <= ~din_n;
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if (wrab1)
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if (wrab1)
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dram_temp[ 3:0] <= ~din_n;
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dram_temp[ 3:0] <= ~din_n;
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