| Line 35... |
Line 35... |
port(
|
port(
|
clk : in STD_LOGIC;
|
clk : in STD_LOGIC;
|
rst : in std_logic;
|
rst : in std_logic;
|
dcti : in std_logic_vector(IP_W-1 downto 0);
|
dcti : in std_logic_vector(IP_W-1 downto 0);
|
idv : in STD_LOGIC;
|
idv : in STD_LOGIC;
|
romedatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romedatao : in T_ROM1DATAO;
|
romedatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
romodatao : in T_ROM1DATAO;
|
romedatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
|
romedatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
|
romedatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
|
romedatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
|
romedatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
|
romedatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
|
romedatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
|
romodatao0 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
|
romodatao1 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
|
romodatao2 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
|
romodatao3 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
|
romodatao4 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
|
romodatao5 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
|
romodatao6 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
|
romodatao7 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
|
romodatao8 : in STD_LOGIC_VECTOR(ROMDATA_W-1 downto 0);
|
|
|
|
odv : out STD_LOGIC;
|
odv : out STD_LOGIC;
|
dcto : out std_logic_vector(OP_W-1 downto 0);
|
dcto : out std_logic_vector(OP_W-1 downto 0);
|
romeaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romeaddro : out T_ROM1ADDRO;
|
romeaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
romoaddro : out T_ROM1ADDRO;
|
romeaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
|
romeaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
|
romeaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
|
romeaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
|
romeaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
|
romeaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
|
romeaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
|
romoaddro0 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
|
romoaddro1 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
|
romoaddro2 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
|
romoaddro3 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
|
romoaddro4 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
|
romoaddro5 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
|
romoaddro6 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
|
romoaddro7 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
|
romoaddro8 : out STD_LOGIC_VECTOR(ROMADDR_W-1 downto 0);
|
|
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
|
ramwaddro : out STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
|
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
|
ramdatai : out STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
|
ramwe : out STD_LOGIC;
|
ramwe : out STD_LOGIC;
|
wmemsel : out STD_LOGIC
|
wmemsel : out STD_LOGIC
|
);
|
);
|
| Line 94... |
Line 62... |
signal latchbuf_reg : INPUT_DATA;
|
signal latchbuf_reg : INPUT_DATA;
|
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
signal col_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
signal row_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
signal rowr_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
signal inpcnt_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
signal ramdatai_s : STD_LOGIC_VECTOR(RAMDATA_W-1 downto 0);
|
|
signal ramwe_s : STD_LOGIC;
|
signal ramwe_s : STD_LOGIC;
|
signal wmemsel_reg : STD_LOGIC;
|
signal wmemsel_reg : STD_LOGIC;
|
signal stage2_reg : STD_LOGIC;
|
signal stage2_reg : STD_LOGIC;
|
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
|
signal stage2_cnt_reg : UNSIGNED(RAMADRR_W-1 downto 0);
|
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
signal col_2_reg : UNSIGNED(RAMADRR_W/2-1 downto 0);
|
begin
|
signal ramwaddro_s : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
|
|
|
ramwe_sg:
|
|
ramwe <= ramwe_s;
|
|
|
|
ramdatai_sg:
|
signal even_not_odd : std_logic;
|
ramdatai <= ramdatai_s;
|
signal even_not_odd_d1 : std_logic;
|
|
signal even_not_odd_d2 : std_logic;
|
|
signal even_not_odd_d3 : std_logic;
|
|
signal ramwe_d1 : STD_LOGIC;
|
|
signal ramwe_d2 : STD_LOGIC;
|
|
signal ramwe_d3 : STD_LOGIC;
|
|
signal ramwe_d4 : STD_LOGIC;
|
|
signal ramwaddro_d1 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
|
|
signal ramwaddro_d2 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
|
|
signal ramwaddro_d3 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
|
|
signal ramwaddro_d4 : STD_LOGIC_VECTOR(RAMADRR_W-1 downto 0);
|
|
signal wmemsel_d1 : STD_LOGIC;
|
|
signal wmemsel_d2 : STD_LOGIC;
|
|
signal wmemsel_d3 : STD_LOGIC;
|
|
signal wmemsel_d4 : STD_LOGIC;
|
|
signal romedatao_d1 : T_ROM1DATAO;
|
|
signal romodatao_d1 : T_ROM1DATAO;
|
|
signal romedatao_d2 : T_ROM1DATAO;
|
|
signal romodatao_d2 : T_ROM1DATAO;
|
|
signal romedatao_d3 : T_ROM1DATAO;
|
|
signal romodatao_d3 : T_ROM1DATAO;
|
|
signal dcto_1 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
|
|
signal dcto_2 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
|
|
signal dcto_3 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
|
|
signal dcto_4 : STD_LOGIC_VECTOR(DA_W-1 downto 0);
|
|
|
-- temporary
|
begin
|
odv_sg:
|
|
odv <= ramwe_s;
|
|
dcto_sg:
|
|
dcto <= ramdatai_s(RAMDATA_W-1) & ramdatai_s(RAMDATA_W-1) & ramdatai_s;
|
|
|
|
wmemsel_sg:
|
ramwaddro <= ramwaddro_d4;
|
wmemsel <= wmemsel_reg;
|
ramwe <= ramwe_d4;
|
|
ramdatai <= dcto_4(DA_W-1 downto 12);
|
|
wmemsel <= wmemsel_d4;
|
|
|
process(clk)
|
process(clk,rst)
|
begin
|
begin
|
if clk = '1' and clk'event then
|
|
if rst = '1' then
|
if rst = '1' then
|
inpcnt_reg <= (others => '0');
|
inpcnt_reg <= (others => '0');
|
latchbuf_reg <= (others => (others => '0'));
|
latchbuf_reg <= (others => (others => '0'));
|
databuf_reg <= (others => (others => '0'));
|
databuf_reg <= (others => (others => '0'));
|
stage2_reg <= '0';
|
stage2_reg <= '0';
|
stage2_cnt_reg <= (others => '1');
|
stage2_cnt_reg <= (others => '1');
|
ramdatai_s <= (others => '0');
|
|
ramwe_s <= '0';
|
ramwe_s <= '0';
|
ramwaddro <= (others => '0');
|
ramwaddro_s <= (others => '0');
|
col_reg <= (others => '0');
|
col_reg <= (others => '0');
|
row_reg <= (others => '0');
|
row_reg <= (others => '0');
|
wmemsel_reg <= '0';
|
wmemsel_reg <= '0';
|
col_2_reg <= (others => '0');
|
col_2_reg <= (others => '0');
|
else
|
elsif clk = '1' and clk'event then
|
|
|
stage2_reg <= '0';
|
stage2_reg <= '0';
|
ramwe_s <= '0';
|
ramwe_s <= '0';
|
|
|
--------------------------------
|
--------------------------------
|
-- 1st stage
|
-- 1st stage
|
| Line 169... |
Line 152... |
--------------------------------
|
--------------------------------
|
-- 2nd stage
|
-- 2nd stage
|
--------------------------------
|
--------------------------------
|
if stage2_cnt_reg < N then
|
if stage2_cnt_reg < N then
|
|
|
if stage2_cnt_reg(0) = '0' then
|
|
ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
|
|
(RESIZE(SIGNED(romedatao0),DA_W) +
|
|
(RESIZE(SIGNED(romedatao1),DA_W-1) & '0') +
|
|
(RESIZE(SIGNED(romedatao2),DA_W-2) & "00") +
|
|
(RESIZE(SIGNED(romedatao3),DA_W-3) & "000") +
|
|
(RESIZE(SIGNED(romedatao4),DA_W-4) & "0000") +
|
|
(RESIZE(SIGNED(romedatao5),DA_W-5) & "00000") +
|
|
(RESIZE(SIGNED(romedatao6),DA_W-6) & "000000") +
|
|
(RESIZE(SIGNED(romedatao7),DA_W-7) & "0000000") -
|
|
(RESIZE(SIGNED(romedatao8),DA_W-8) & "00000000"),
|
|
DA_W)(DA_W-1 downto 12));
|
|
else
|
|
ramdatai_s <= STD_LOGIC_VECTOR(RESIZE
|
|
(RESIZE(SIGNED(romodatao0),DA_W) +
|
|
(RESIZE(SIGNED(romodatao1),DA_W-1) & '0') +
|
|
(RESIZE(SIGNED(romodatao2),DA_W-2) & "00") +
|
|
(RESIZE(SIGNED(romodatao3),DA_W-3) & "000") +
|
|
(RESIZE(SIGNED(romodatao4),DA_W-4) & "0000") +
|
|
(RESIZE(SIGNED(romodatao5),DA_W-5) & "00000") +
|
|
(RESIZE(SIGNED(romodatao6),DA_W-6) & "000000") +
|
|
(RESIZE(SIGNED(romodatao7),DA_W-7) & "0000000") -
|
|
(RESIZE(SIGNED(romodatao8),DA_W-8) & "00000000"),
|
|
DA_W)(DA_W-1 downto 12));
|
|
end if;
|
|
|
|
stage2_cnt_reg <= stage2_cnt_reg + 1;
|
stage2_cnt_reg <= stage2_cnt_reg + 1;
|
|
|
-- write RAM
|
-- write RAM
|
ramwe_s <= '1';
|
ramwe_s <= '1';
|
-- reverse col/row order for transposition purpose
|
-- reverse col/row order for transposition purpose
|
ramwaddro <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
|
ramwaddro_s <= STD_LOGIC_VECTOR(col_2_reg & row_reg);
|
-- increment column counter
|
-- increment column counter
|
col_reg <= col_reg + 1;
|
col_reg <= col_reg + 1;
|
col_2_reg <= col_2_reg + 1;
|
col_2_reg <= col_2_reg + 1;
|
|
|
-- finished processing one input row
|
-- finished processing one input row
|
| Line 223... |
Line 180... |
stage2_cnt_reg <= (others => '0');
|
stage2_cnt_reg <= (others => '0');
|
col_reg <= (0=>'1',others => '0');
|
col_reg <= (0=>'1',others => '0');
|
col_2_reg <= (others => '0');
|
col_2_reg <= (others => '0');
|
end if;
|
end if;
|
----------------------------------
|
----------------------------------
|
|
|
|
|
|
end if;
|
|
end process;
|
|
|
|
-- output data pipeline
|
|
p_data_out_pipe : process(CLK, RST)
|
|
begin
|
|
if RST = '1' then
|
|
even_not_odd <= '0';
|
|
even_not_odd_d1 <= '0';
|
|
even_not_odd_d2 <= '0';
|
|
even_not_odd_d3 <= '0';
|
|
ramwe_d1 <= '0';
|
|
ramwe_d2 <= '0';
|
|
ramwe_d3 <= '0';
|
|
ramwe_d4 <= '0';
|
|
ramwaddro_d1 <= (others => '0');
|
|
ramwaddro_d2 <= (others => '0');
|
|
ramwaddro_d3 <= (others => '0');
|
|
ramwaddro_d4 <= (others => '0');
|
|
wmemsel_d1 <= '0';
|
|
wmemsel_d2 <= '0';
|
|
wmemsel_d3 <= '0';
|
|
wmemsel_d4 <= '0';
|
|
dcto_1 <= (others => '0');
|
|
dcto_2 <= (others => '0');
|
|
dcto_3 <= (others => '0');
|
|
dcto_4 <= (others => '0');
|
|
elsif CLK'event and CLK = '1' then
|
|
even_not_odd <= stage2_cnt_reg(0);
|
|
even_not_odd_d1 <= even_not_odd;
|
|
even_not_odd_d2 <= even_not_odd_d1;
|
|
even_not_odd_d3 <= even_not_odd_d2;
|
|
ramwe_d1 <= ramwe_s;
|
|
ramwe_d2 <= ramwe_d1;
|
|
ramwe_d3 <= ramwe_d2;
|
|
ramwe_d4 <= ramwe_d3;
|
|
ramwaddro_d1 <= ramwaddro_s;
|
|
ramwaddro_d2 <= ramwaddro_d1;
|
|
ramwaddro_d3 <= ramwaddro_d2;
|
|
ramwaddro_d4 <= ramwaddro_d3;
|
|
wmemsel_d1 <= wmemsel_reg;
|
|
wmemsel_d2 <= wmemsel_d1;
|
|
wmemsel_d3 <= wmemsel_d2;
|
|
wmemsel_d4 <= wmemsel_d3;
|
|
|
|
if even_not_odd = '0' then
|
|
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
|
|
(RESIZE(SIGNED(romedatao(0)),DA_W) +
|
|
(RESIZE(SIGNED(romedatao(1)),DA_W-1) & '0') +
|
|
(RESIZE(SIGNED(romedatao(2)),DA_W-2) & "00"),
|
|
DA_W));
|
|
else
|
|
dcto_1 <= STD_LOGIC_VECTOR(RESIZE
|
|
(RESIZE(SIGNED(romodatao(0)),DA_W) +
|
|
(RESIZE(SIGNED(romodatao(1)),DA_W-1) & '0') +
|
|
(RESIZE(SIGNED(romodatao(2)),DA_W-2) & "00"),
|
|
DA_W));
|
|
end if;
|
|
|
|
if even_not_odd_d1 = '0' then
|
|
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
|
|
(signed(dcto_1) +
|
|
(RESIZE(SIGNED(romedatao_d1(3)),DA_W-3) & "000") +
|
|
(RESIZE(SIGNED(romedatao_d1(4)),DA_W-4) & "0000"),
|
|
DA_W));
|
|
else
|
|
dcto_2 <= STD_LOGIC_VECTOR(RESIZE
|
|
(signed(dcto_1) +
|
|
(RESIZE(SIGNED(romodatao_d1(3)),DA_W-3) & "000") +
|
|
(RESIZE(SIGNED(romodatao_d1(4)),DA_W-4) & "0000"),
|
|
DA_W));
|
|
end if;
|
|
|
|
if even_not_odd_d2 = '0' then
|
|
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
|
|
(signed(dcto_2) +
|
|
(RESIZE(SIGNED(romedatao_d2(5)),DA_W-5) & "00000") +
|
|
(RESIZE(SIGNED(romedatao_d2(6)),DA_W-6) & "000000"),
|
|
DA_W));
|
|
else
|
|
dcto_3 <= STD_LOGIC_VECTOR(RESIZE
|
|
(signed(dcto_2) +
|
|
(RESIZE(SIGNED(romodatao_d2(5)),DA_W-5) & "00000") +
|
|
(RESIZE(SIGNED(romodatao_d2(6)),DA_W-6) & "000000"),
|
|
DA_W));
|
|
end if;
|
|
|
|
if even_not_odd_d3 = '0' then
|
|
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
|
|
(signed(dcto_3) +
|
|
(RESIZE(SIGNED(romedatao_d3(7)),DA_W-7) & "0000000") -
|
|
(RESIZE(SIGNED(romedatao_d3(8)),DA_W-8) & "00000000"),
|
|
DA_W));
|
|
else
|
|
dcto_4 <= STD_LOGIC_VECTOR(RESIZE
|
|
(signed(dcto_3) +
|
|
(RESIZE(SIGNED(romodatao_d3(7)),DA_W-7) & "0000000") -
|
|
(RESIZE(SIGNED(romodatao_d3(8)),DA_W-8) & "00000000"),
|
|
DA_W));
|
end if;
|
end if;
|
end if;
|
end if;
|
end process;
|
end process;
|
|
|
-- read precomputed MAC results from LUT
|
-- read precomputed MAC results from LUT
|
romeaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
p_romaddr : process(CLK, RST)
|
databuf_reg(0)(0) &
|
begin
|
databuf_reg(1)(0) &
|
if RST = '1' then
|
databuf_reg(2)(0) &
|
romeaddro <= (others => (others => '0'));
|
databuf_reg(3)(0);
|
romoaddro <= (others => (others => '0'));
|
romeaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
elsif CLK'event and CLK = '1' then
|
databuf_reg(0)(1) &
|
for i in 0 to 8 loop
|
databuf_reg(1)(1) &
|
-- even
|
databuf_reg(2)(1) &
|
romeaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
databuf_reg(3)(1);
|
databuf_reg(0)(i) &
|
romeaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
databuf_reg(1)(i) &
|
databuf_reg(0)(2) &
|
databuf_reg(2)(i) &
|
databuf_reg(1)(2) &
|
databuf_reg(3)(i);
|
databuf_reg(2)(2) &
|
|
databuf_reg(3)(2);
|
|
romeaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(0)(3) &
|
|
databuf_reg(1)(3) &
|
|
databuf_reg(2)(3) &
|
|
databuf_reg(3)(3);
|
|
romeaddro4 <= STD_LOGIC_VECTOR( col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(0)(4) &
|
|
databuf_reg(1)(4) &
|
|
databuf_reg(2)(4) &
|
|
databuf_reg(3)(4);
|
|
romeaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(0)(5) &
|
|
databuf_reg(1)(5) &
|
|
databuf_reg(2)(5) &
|
|
databuf_reg(3)(5);
|
|
romeaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(0)(6) &
|
|
databuf_reg(1)(6) &
|
|
databuf_reg(2)(6) &
|
|
databuf_reg(3)(6);
|
|
romeaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(0)(7) &
|
|
databuf_reg(1)(7) &
|
|
databuf_reg(2)(7) &
|
|
databuf_reg(3)(7);
|
|
romeaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(0)(8) &
|
|
databuf_reg(1)(8) &
|
|
databuf_reg(2)(8) &
|
|
databuf_reg(3)(8);
|
|
|
|
-- odd
|
-- odd
|
romoaddro0 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
romoaddro(i) <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
databuf_reg(4)(0) &
|
databuf_reg(4)(i) &
|
databuf_reg(5)(0) &
|
databuf_reg(5)(i) &
|
databuf_reg(6)(0) &
|
databuf_reg(6)(i) &
|
databuf_reg(7)(0);
|
databuf_reg(7)(i);
|
romoaddro1 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
end loop;
|
databuf_reg(4)(1) &
|
end if;
|
databuf_reg(5)(1) &
|
end process;
|
databuf_reg(6)(1) &
|
|
databuf_reg(7)(1);
|
|
romoaddro2 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(4)(2) &
|
|
databuf_reg(5)(2) &
|
|
databuf_reg(6)(2) &
|
|
databuf_reg(7)(2);
|
|
romoaddro3 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(4)(3) &
|
|
databuf_reg(5)(3) &
|
|
databuf_reg(6)(3) &
|
|
databuf_reg(7)(3);
|
|
romoaddro4 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(4)(4) &
|
|
databuf_reg(5)(4) &
|
|
databuf_reg(6)(4) &
|
|
databuf_reg(7)(4);
|
|
romoaddro5 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(4)(5) &
|
|
databuf_reg(5)(5) &
|
|
databuf_reg(6)(5) &
|
|
databuf_reg(7)(5);
|
|
romoaddro6 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(4)(6) &
|
|
databuf_reg(5)(6) &
|
|
databuf_reg(6)(6) &
|
|
databuf_reg(7)(6);
|
|
romoaddro7 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(4)(7) &
|
|
databuf_reg(5)(7) &
|
|
databuf_reg(6)(7) &
|
|
databuf_reg(7)(7);
|
|
romoaddro8 <= STD_LOGIC_VECTOR(col_reg(RAMADRR_W/2-1 downto 1)) &
|
|
databuf_reg(4)(8) &
|
|
databuf_reg(5)(8) &
|
|
databuf_reg(6)(8) &
|
|
databuf_reg(7)(8);
|
|
|
|
|
p_romdatao_d1 : process(CLK, RST)
|
|
begin
|
|
if RST = '1' then
|
|
romedatao_d1 <= (others => (others => '0'));
|
|
romodatao_d1 <= (others => (others => '0'));
|
|
romedatao_d2 <= (others => (others => '0'));
|
|
romodatao_d2 <= (others => (others => '0'));
|
|
romedatao_d3 <= (others => (others => '0'));
|
|
romodatao_d3 <= (others => (others => '0'));
|
|
elsif CLK'event and CLK = '1' then
|
|
romedatao_d1 <= romedatao;
|
|
romodatao_d1 <= romodatao;
|
|
romedatao_d2 <= romedatao_d1;
|
|
romodatao_d2 <= romodatao_d1;
|
|
romedatao_d3 <= romedatao_d2;
|
|
romodatao_d3 <= romodatao_d2;
|
|
end if;
|
|
end process;
|
|
|
end RTL;
|
end RTL;
|
--------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------
|
|
|
No newline at end of file
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No newline at end of file
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