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[/] [mips32r1/] [trunk/] [Hardware/] [MIPS32_Standalone/] [MIPS_Parameters.v] - Diff between revs 3 and 9

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/*** Processor Endianness ***
/*** Processor Endianness ***
 
 
     MIPS32 allows user-mode addresses to be configured as big- or little-endian. For simplicity
     The MIPS Configuration Register (CP0 Register 16 Select 0) specifies the processor's
     reasons, this processor fixes the endianness to little endian. To add support for both
     endianness. A processor in user mode may switch to reverse endianness, which will be
     modes, the Data Memory Controller should be updated as well as CP0, which should change
     the opposite of this parameter.
     the 'RE' bit in the Status register from a wire to a writable register.
 
*/
*/
parameter Big_Endian = 0;
parameter Big_Endian = 1;
 
 
 
 
 
 
/*** Encodings for MIPS32 Release 1 Architecture ***/
/*** Encodings for MIPS32 Release 1 Architecture ***/
 
 

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