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https://opencores.org/ocsvn/mips32r1/mips32r1/trunk
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Rev 7 |
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*
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*
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* Modification History:
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* Modification History:
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* Rev Date Initials Description of Change
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* Rev Date Initials Description of Change
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* 1.0 23-Jul-2011 GEA Initial design.
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* 1.0 23-Jul-2011 GEA Initial design.
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* 2.0 26-May-2012 GEA Release version with CP0.
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* 2.0 26-May-2012 GEA Release version with CP0.
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* 2.01 1-Nov-2012 GEA Fixed issue with Jal.
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*
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*
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* Standards/Formatting:
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* Standards/Formatting:
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* Verilog 2001, 4 soft tab, wide column.
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* Verilog 2001, 4 soft tab, wide column.
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*
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*
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* Description:
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* Description:
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Mux4 #(.WIDTH(32)) IDRsFwd_Mux (
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Mux4 #(.WIDTH(32)) IDRsFwd_Mux (
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.sel (ID_RsFwdSel),
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.sel (ID_RsFwdSel),
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.in0 (ID_ReadData1_RF),
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.in0 (ID_ReadData1_RF),
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.in1 (M_ALUResult),
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.in1 (M_ALUResult),
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.in2 (WB_WriteData),
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.in2 (WB_WriteData),
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.in3 (ID_PCAdd4),
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.in3 (32'hxxxxxxxx),
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.out (ID_ReadData1_End)
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.out (ID_ReadData1_End)
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);
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);
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/*** ID Rt Forwarding/CP0 Mfc0 Mux ***/
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/*** ID Rt Forwarding/CP0 Mfc0 Mux ***/
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Mux4 #(.WIDTH(32)) IDRtFwd_Mux (
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Mux4 #(.WIDTH(32)) IDRtFwd_Mux (
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Mux4 #(.WIDTH(32)) EXRsFwd_Mux (
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Mux4 #(.WIDTH(32)) EXRsFwd_Mux (
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.sel (EX_RsFwdSel),
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.sel (EX_RsFwdSel),
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.in0 (EX_ReadData1_PR),
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.in0 (EX_ReadData1_PR),
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.in1 (M_ALUResult),
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.in1 (M_ALUResult),
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.in2 (WB_WriteData),
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.in2 (WB_WriteData),
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.in3 (32'hxxxxxxxx),
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.in3 (EX_RestartPC),
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.out (EX_ReadData1_Fwd)
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.out (EX_ReadData1_Fwd)
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);
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);
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/*** EX Rt Forwarding / Link Mux ***/
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/*** EX Rt Forwarding / Link Mux ***/
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Mux4 #(.WIDTH(32)) EXRtFwdLnk_Mux (
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Mux4 #(.WIDTH(32)) EXRtFwdLnk_Mux (
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.sel (EX_RtFwdSel),
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.sel (EX_RtFwdSel),
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.in0 (EX_ReadData2_PR),
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.in0 (EX_ReadData2_PR),
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.in1 (M_ALUResult),
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.in1 (M_ALUResult),
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.in2 (WB_WriteData),
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.in2 (WB_WriteData),
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.in3 (32'h00000004),
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.in3 (32'h00000008),
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.out (EX_ReadData2_Fwd)
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.out (EX_ReadData2_Fwd)
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);
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);
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/*** EX ALU Immediate Mux ***/
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/*** EX ALU Immediate Mux ***/
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Mux2 #(.WIDTH(32)) EXALUImm_Mux (
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Mux2 #(.WIDTH(32)) EXALUImm_Mux (
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