| Line 156... |
Line 156... |
signal write_in_adc: std_logic;
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signal write_in_adc: std_logic;
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Flags
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-- Flags
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signal running: std_logic;
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signal status: std_logic_vector(1 downto 0);
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signal next_status1: std_logic;
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signal stop: std_logic;
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signal stop: std_logic;
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signal start: std_logic;
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signal start: std_logic;
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signal continuous: std_logic;
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signal continuous: std_logic;
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Line 313... |
trigger_level_O => reg_trigger_level,
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trigger_level_O => reg_trigger_level,
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trigger_offset_O => reg_trigger_offset,
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trigger_offset_O => reg_trigger_offset,
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trigger_channel_O => reg_trigger_channel,
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trigger_channel_O => reg_trigger_channel,
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error_number_I => "000", -- not implemented yet
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error_number_I => "000", -- not implemented yet
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error_flag_I => '0', -- not implemented yet
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adc_conf_O => dat_to_adc,
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adc_conf_O => dat_to_adc,
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start_O => start,
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start_O => start,
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continuous_O => continuous,
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continuous_O => continuous,
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running_I => running,
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status_I => status,
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write_in_adc_O => write_in_adc,
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write_in_adc_O => write_in_adc,
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stop_O => stop
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stop_O => stop
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);
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);
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------------------------------------------------------------------------------------------------
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------------------------------------------------------------------------------------------------
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| Line 358... |
Line 358... |
chsel_reset <= '0';
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chsel_reset <= '0';
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trigger_reset <= '1';
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trigger_reset <= '1';
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trigger_en <= '-';
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trigger_en <= '-';
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running <= '1';
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status(0) <= '1';
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next_status1 <= not(next_status1); -- will be changed every buffer full read
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strobe_adc <= '0';
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strobe_adc <= '0';
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-- -- -- --
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-- -- -- --
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next_state <= ST_RUNNING;
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next_state <= ST_RUNNING;
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-- if there is an error manager, influde an if for errors in parameters
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when ST_RUNNING =>
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when ST_RUNNING =>
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memwr_reset <= '0';
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memwr_reset <= '0';
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Line 384... |
chsel_reset <= '0';
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chsel_reset <= '0';
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trigger_reset <= '0';
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trigger_reset <= '0';
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trigger_en <= reg_trigger_en and memwr_in_ack_mem;
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trigger_en <= reg_trigger_en and memwr_in_ack_mem;
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running <= '1';
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status(0) <= '1';
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next_status1 <= status(1);
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strobe_adc <= '0';
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strobe_adc <= '0';
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-- -- -- --
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-- -- -- --
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-- if there is an error manager, influde an if for errors in running, etc...
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if outmgr_finish = '1' then
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if outmgr_finish = '1' then
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if continuous = '1' then
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if continuous = '1' then
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next_state <= ST_INIT;
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next_state <= ST_INIT;
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else
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else
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next_state <= ST_IDLE;
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next_state <= ST_IDLE;
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Line 412... |
chsel_reset <= '1';
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chsel_reset <= '1';
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trigger_reset <= '1';
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trigger_reset <= '1';
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trigger_en <= '-';
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trigger_en <= '-';
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running <= '1'; -- aviod an ack if there is a read/write from port
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status(0) <= '1'; -- aviod an ack if there is a read/write from port
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next_status1 <= status(1);
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strobe_adc <= '0';
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strobe_adc <= '0';
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-- -- -- --
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-- -- -- --
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next_state <= ST_ADCWRITE;
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next_state <= ST_ADCWRITE;
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Line 432... |
chsel_reset <= '1';
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chsel_reset <= '1';
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trigger_reset <= '1';
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trigger_reset <= '1';
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trigger_en <= '-';
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trigger_en <= '-';
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running <= '1'; -- aviod an ack if there is a read/write from port
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status(0) <= '1'; -- aviod an ack if there is a read/write from port
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next_status1 <= status(1);
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strobe_adc <= '1';
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strobe_adc <= '1';
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-- -- -- --
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-- -- -- --
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if ACK_I_daq = '1' then
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if ACK_I_daq = '1' then
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Line 456... |
chsel_reset <= '1';
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chsel_reset <= '1';
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trigger_reset <= '1';
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trigger_reset <= '1';
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trigger_en <= '-';
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trigger_en <= '-';
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running <= '0';
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status(0) <= '0';
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next_status1 <= '0'; -- or error when there is an error manager
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strobe_adc <= '0';
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strobe_adc <= '0';
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-- -- -- --
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-- -- -- --
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next_state <= ST_IDLE;
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next_state <= ST_IDLE;
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Line 472... |
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P_sm_clkd: process (RST_I_daq, stop, start, CLK_I_daq, next_state, write_in_adc)
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P_sm_clkd: process (RST_I_daq, stop, start, CLK_I_daq, next_state, write_in_adc)
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begin
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begin
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if RST_I_daq = '1' or stop = '1' then
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if RST_I_daq = '1' then
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present_state <= ST_IDLE;
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status(1) <= '0';
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elsif stop = '1' then
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present_state <= ST_IDLE;
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present_state <= ST_IDLE;
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elsif write_in_adc = '1' then
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elsif write_in_adc = '1' then
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present_state <= ST_ADCWRITE_INIT;
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present_state <= ST_ADCWRITE_INIT;
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elsif start = '1' and present_state /= ST_ADCWRITE and present_state /= ST_ADCWRITE_INIT then
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elsif start = '1' and present_state /= ST_ADCWRITE and present_state /= ST_ADCWRITE_INIT then
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present_state <= ST_INIT;
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present_state <= ST_INIT;
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elsif CLK_I_daq'event and CLK_I_daq = '1' then
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elsif CLK_I_daq'event and CLK_I_daq = '1' then
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present_state <= next_state;
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present_state <= next_state;
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status(1) <= next_status1;
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end if;
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end if;
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end process;
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end process;
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