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Line 27... |
----------------------------------------------------------------------------------------------------
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----------------------------------------------------------------------------------------------------
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--==================================================================================================
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--==================================================================================================
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-- TO DO
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-- TO DO
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-- NO Speed up address_counter
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-- · (NO) Speed up address_counter
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-- OK Full test of new architecture
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-- · (OK) Full test of new architecture
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-- OK Fix default value of s_finish signal
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-- · (OK) Fix default value of s_finish signal
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-- · General speed up
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-- · General speed up
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--==================================================================================================
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--==================================================================================================
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library ieee;
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library ieee;
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Line 105... |
architecture ARCH22 of ctrl_output_manager is
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architecture ARCH22 of ctrl_output_manager is
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signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
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signal address_counter: std_logic_vector(MEM_ADD_WIDTH - 1 downto 0);
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signal enable_read: std_logic;
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signal enable_read: std_logic;
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signal enable_count: std_logic;
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signal enable_count: std_logic;
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signal enable_strobe: std_logic;
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signal s_finish: std_logic; -- register previous (and equal) to output
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signal s_finish: std_logic; -- register previous (and equal) to output
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signal init: std_logic; -- register
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signal init: std_logic; -- register
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signal same_address: std_logic;
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begin
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begin
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Wishbone signals
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-- Wishbone signals
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Line 124... |
WE_O_mem <= '0' ;
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WE_O_mem <= '0' ;
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Status signals
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-- Status signals
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-- there is an init signal because in the first read, address_counter may be = to pause_address_I
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-- there is an init signal because in the first read, address_counter may be = to pause_address_I
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enable_read <= '1' when enable_I = '1' and WE_I_port = '0' and s_finish = '0' and
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P_pause: process (CLK_I, RST_I, address_counter, pause_address_I)
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(address_counter /= pause_address_I or init = '1')
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begin
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if CLK_I'event and CLK_I = '1' then
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if RST_I = '1' then
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same_address <= '0';
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elsif address_counter = pause_address_I then
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same_address <= '1';
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else
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same_address <= '0';
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end if;
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end if;
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end process;
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P_flags: process(CLK_I, RST_I, enable_I, enable_count, load_I)
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begin
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if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
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-- when enable is '0', finish_O must be 0 again
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if RST_I = '1' or enable_I = '0' then
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init <= '1';
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enable_strobe <= '0';
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elsif (load_I = '1' and enable_I = '1') then
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enable_strobe <= '1';
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init <= '1';
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elsif enable_count = '1' then
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init <= '0';
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end if;
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end if;
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end process;
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enable_read <= '1' when WE_I_port = '0' and s_finish = '0' and
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(same_address = '0' or init = '1') and enable_strobe = '1'
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else '0';
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else '0';
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enable_count <= CYC_I_port and STB_I_port and ACK_I_mem and enable_read;
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enable_count <= CYC_I_port and STB_I_port and ACK_I_mem and enable_read;
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finish_O <= s_finish;
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s_finish <= '1' when address_counter = initial_address_I and init = '0' else
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s_finish <= '1' when address_counter = initial_address_I and init = '0' else
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'0';
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'0';
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finish_O <= s_finish;
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-- P_finish: process ( CLK_I, RST_I, address_counter, initial_address_I, load_I)
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-- begin
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-- if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
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-- if RST_I = '1' then
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-- --s_finish <= '0'; -- !! enable signal must be '0' until load
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-- init <= '0';
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-- elsif load_I = '1' then
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-- --s_finish <= '0';
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-- init <= '1';
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-- -- elsif address_counter + 1 = initial_address_I then
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-- -- s_finish <= '1';
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-- -- init <= '0';
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-- elsif enable_count = '1' then
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-- init <= '0';
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-- end if;
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-- end if;
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-- end process;
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--------------------------------------------------------------------------------------------------
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--------------------------------------------------------------------------------------------------
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-- Address counter
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-- Address counter
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P_count: process(CLK_I, RST_I, address_counter, enable_count, load_I)
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P_count: process(CLK_I, RST_I, address_counter, enable_count, load_I)
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begin
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begin
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if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
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if CLK_I'event and CLK_I = '1' and CLK_I'LAST_VALUE = '0' then
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if RST_I = '1' then
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if RST_I = '1' then
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address_counter <= (others => '0');
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address_counter <= (others => '0');
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init <= '1';
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elsif load_I = '1' and enable_I = '1' then
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elsif load_I = '1' then
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address_counter <= initial_address_I;
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address_counter <= initial_address_I;
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init <= '1';
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elsif enable_count = '1' and address_counter >= biggest_address_I then
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elsif enable_count = '1' and address_counter >= biggest_address_I then
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address_counter <= (others => '0');
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address_counter <= (others => '0');
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elsif enable_count = '1' then
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elsif enable_count = '1' then
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address_counter <= address_counter + 1;
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address_counter <= address_counter + 1;
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init <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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end process;
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end architecture;
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end architecture;
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No newline at end of file
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No newline at end of file
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