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[/] [modular_oscilloscope/] [trunk/] [hdl/] [ctrl/] [trigger_manager.vhd] - Diff between revs 48 and 55

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Rev 48 Rev 55
Line 77... Line 77...
  signal offset_sign: std_logic;
  signal offset_sign: std_logic;
  signal truncate: std_logic;
  signal truncate: std_logic;
  signal selected_address: std_logic_vector(MEM_ADD_WIDTH -1 downto 0);
  signal selected_address: std_logic_vector(MEM_ADD_WIDTH -1 downto 0);
  signal selected_address_reg: std_logic_vector(MEM_ADD_WIDTH -1 downto 0);
  signal selected_address_reg: std_logic_vector(MEM_ADD_WIDTH -1 downto 0);
 
 
 
  signal full_buffer: std_logic;
 
 
begin
begin
 
 
  --------------------------------------------------------------------------------------------------
  --------------------------------------------------------------------------------------------------
  -- Output address selection
  -- Output address selection
Line 99... Line 100...
  add_plus_off_plus_fa_sign <= add_plus_off_plus_fa (MEM_ADD_WIDTH);
  add_plus_off_plus_fa_sign <= add_plus_off_plus_fa (MEM_ADD_WIDTH);
 
 
  truncate <= (offset_sign and  add_plus_off_sign) or
  truncate <= (offset_sign and  add_plus_off_sign) or
              (not(offset_sign) and not(add_plus_off_plus_fa_sign));
              (not(offset_sign) and not(add_plus_off_plus_fa_sign));
 
 
 
 
  with truncate select
  with truncate select
    selected_address <= std_logic_vector(add_plus_off_plus_fa(MEM_ADD_WIDTH - 1 downto 0))
    selected_address <= std_logic_vector(add_plus_off_plus_fa(MEM_ADD_WIDTH - 1 downto 0))
                          when '1',
                          when '1',
                        std_logic_vector(add_plus_off(MEM_ADD_WIDTH - 1 downto 0))
                        std_logic_vector(add_plus_off(MEM_ADD_WIDTH - 1 downto 0))
                          when others;
                          when others;
Line 125... Line 125...
        selected_address_reg <= (others => '0');
        selected_address_reg <= (others => '0');
      elsif enable_I = '1' then
      elsif enable_I = '1' then
 
 
        if channel_I = trig_channel_I then
        if channel_I = trig_channel_I then
          if  (higher_reg = '0' xor falling_I = '1') and
          if  (higher_reg = '0' xor falling_I = '1') and
              (higher = '1' xor falling_I = '1') and pre_trigger = '0'
              (higher = '1' xor falling_I = '1') and pre_trigger = '0' and full_buffer = '1'
              then -- trigger!
              then -- trigger!
            pre_trigger <= '1';
            pre_trigger <= '1';
            selected_address_reg <= selected_address;
            selected_address_reg <= selected_address;
            if offset_sign = '1' or unsigned(offset_I) = 0 then
            if offset_sign = '1' or unsigned(offset_I) = 0 then
              trigger_O <= '1';
              trigger_O <= '1';
            end if;
            end if;
          end if;
          end if;
          higher_reg <= higher;
          higher_reg <= higher; -- higher_reg will be the previous higher 
        end if;
        end if;
 
 
        if pre_trigger = '1' and selected_address_reg = address_I then
        if pre_trigger = '1' and selected_address_reg = address_I then
          -- if offset > 0 then trigger will wait until address_I equals trigger address plus offset
          -- if offset > 0 then trigger will wait until address_I equals trigger address plus offset
            trigger_O <= '1';
            trigger_O <= '1';
Line 145... Line 145...
 
 
      end if;
      end if;
    end if;
    end if;
  end process;
  end process;
 
 
 
  -- When using negative offset for buffer, buffer must be filled before set trigger 
 
  P_wait_buffer_full: process (clk_I)
 
  begin
 
    if clk_I'event and clk_I = '1' then
 
      if reset_I = '1' then
 
        full_buffer <= '0';
 
      elsif enable_I = '1' and (offset_sign = '0' or add_plus_off_sign = '0') and
 
      full_buffer <= '0' then
 
        full_buffer <= '1';
 
      end if;
 
    end if;
 
  end process;
 
 
  -- t pt f /f xor1 xor2 and
  -- t pt f /f xor1 xor2 and
  -- 000 1 0 1 
  -- 000 1 0 1 
  -- 001 0 1 0 
  -- 001 0 1 0 
  -- 010 1 0 0     
  -- 010 1 0 0     
Line 157... Line 168...
  -- 100 1 1 1 1 
  -- 100 1 1 1 1 
  -- 101 0 0 0  
  -- 101 0 0 0  
  -- 110 1 1 0  
  -- 110 1 1 0  
  -- 111 0 0 1  
  -- 111 0 0 1  
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
end architecture;
end architecture;
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