URL https://opencores.org/ocsvn/modular_oscilloscope/modular_oscilloscope/trunk

Subversion Repositories modular_oscilloscope

[/] [modular_oscilloscope/] [trunk/] [hdl/] [daq/] [daq.vhd] - Diff between revs 39 and 57

Rev 39	Rev 57
Line 48...	Line 48...
`use IEEE.NUMERIC_STD.ALL;`	`use IEEE.NUMERIC_STD.ALL;`
`--use work.adq_pgk.all;`	`--use work.adq_pgk.all;`

`entity daq is`	`entity daq is`
`generic (`	`generic (`
`DEFALT_CONFIG : std_logic_vector := "0000100000000000"`	`DEFALT_CONFIG : std_logic_vector := "0000001000000000"`
	`-- 5432109876543210`
`-- bits 8 a 0 clk_pre_scaler`	`-- bits 8 a 0 clk_pre_scaler`
`-- bits 9 clk_pre_scaler_ena`	`-- bits 9 clk_pre_scaler_ena`
`-- bit 10 adc sleep`	`-- bit 10 adc sleep`
`-- bit 11 adc_chip_sel`	`-- bit 11 adc_chip_sel`
`-- bits 12 a 15 sin usar`	`-- bits 12 a 15 sin usar`
Line 65...	Line 66...
`-- Externo`	`-- Externo`
`adc_data_I: in std_logic_vector (9 downto 0);`	`adc_data_I: in std_logic_vector (9 downto 0);`
`adc_sel_O: out std_logic;`	`adc_sel_O: out std_logic;`
`adc_clk_O: out std_logic;`	`adc_clk_O: out std_logic;`
`adc_sleep_O: out std_logic;`	`adc_sleep_O: out std_logic;`
`adc_chip_sel_O: out std_logic;`	`adc_chip_sel_O: out std_logic; -- '1' disable, '0' select`


`-- Interno`	`-- Interno`
`RST_I: in std_logic;`	`RST_I: in std_logic;`
`CLK_I: in std_logic;`	`CLK_I: in std_logic;`