| Line 12... |
Line 12... |
--|
|
--|
|
--|-------------------------------------------------------------------------------------------------
|
--|-------------------------------------------------------------------------------------------------
|
--| File history:
|
--| File history:
|
--| 0.1 | aug-2009 | First release
|
--| 0.1 | aug-2009 | First release
|
----------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------
|
--| Copyright © 2009, Facundo Aguilera.
|
--| Copyright © 2009, Facundo Aguilera (budinero at gmail.com.
|
--|
|
--|
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--| This VHDL design file is an open design; you can redistribute it and/or
|
--| This VHDL design file is an open design; you can redistribute it and/or
|
--| modify it and/or implement it after contacting the author.
|
--| modify it and/or implement it after contacting the author.
|
----------------------------------------------------------------------------------------------------
|
----------------------------------------------------------------------------------------------------
|
|
|
--==================================================================================================
|
--==================================================================================================
|
-- TO DO
|
-- TO DO
|
-- · Full full test
|
-- · Full full test
|
--==================================================================================================
|
--==================================================================================================
|
|
|
|
-- NOTES
|
|
-- · Board clock freq = 25 MHz
|
|
-- · PLL clocks: clk_epp freq = 10 MHz, clk_epp freq = 40 MHz
|
|
|
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
|
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
|
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-->> Virtual clock
|
library ieee;
|
library ieee;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.math_real.all;
|
use ieee.math_real.all;
|
|
|
|
|
|
|
entity ctrl_tb_simple_clock is
|
entity tb_simple_clock is
|
port (
|
port (
|
CLK_PERIOD: in time;-- := 20 ns;
|
CLK_PERIOD: in time;-- := 20 ns;
|
CLK_DUTY: in real; -- := 0.5;
|
CLK_DUTY: in real; -- := 0.5;
|
active: in boolean;
|
active: in boolean;
|
clk_o: out std_logic
|
clk_o: out std_logic
|
);
|
);
|
end entity ctrl_tb_simple_clock ;
|
end entity tb_simple_clock ;
|
|
|
architecture beh of ctrl_tb_simple_clock is
|
architecture beh of tb_simple_clock is
|
begin
|
begin
|
P_main: process
|
P_main: process
|
begin
|
begin
|
wait until active;
|
wait until active;
|
while (active = true) loop
|
while (active = true) loop
|
| Line 57... |
Line 60... |
clk_o <= '0';
|
clk_o <= '0';
|
wait;
|
wait;
|
end process;
|
end process;
|
end architecture beh;
|
end architecture beh;
|
|
|
|
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
|
|
-->> Virtual ADC
|
|
library ieee;
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.std_logic_unsigned.all;
|
|
|
|
entity virtual_adc is
|
|
port (
|
|
clk_I: in std_logic;
|
|
sel_I: in std_logic;
|
|
chip_sel_I: in std_logic;
|
|
sleep_I: in std_logic;
|
|
data_O: out std_logic_vector(9 downto 0)
|
|
);
|
|
end entity virtual_adc ;
|
|
|
|
architecture beh of virtual_adc is
|
|
signal data1: std_logic_vector(9 downto 0) := "0000000001"; -- odd
|
|
signal data2: std_logic_vector(9 downto 0) := (others => '0'); -- pair
|
|
begin
|
|
|
|
P_virtual_adc: process (clk_I, sel_I, chip_sel_I, sleep_I)
|
|
|
|
begin
|
|
if clk_I'event and clk_I = '1' then
|
|
data1 <= data1 + 2;
|
|
data2 <= data2 + 2;
|
|
end if;
|
|
|
|
if sleep_I = '1' or chip_sel_I = '0' then
|
|
data_O <= (others => '0');
|
|
else
|
|
case sel_I is
|
|
when '0' =>
|
|
data_O <= data1;
|
|
when others =>
|
|
data_O <= data2;
|
|
end case;
|
|
end if;
|
|
|
|
end process;
|
|
|
|
end architecture beh;
|
|
|
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
|
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
|
|
-->> Stimulus
|
library ieee, std;
|
library ieee, std;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_unsigned.all;
|
use ieee.std_logic_unsigned.all;
|
use IEEE.NUMERIC_STD.ALL;
|
--use IEEE.NUMERIC_STD.ALL;
|
use ieee.math_real.all;
|
use ieee.math_real.all;
|
|
|
|
|
-- Additional libraries used by Model Under Test.
|
-- Additional libraries used by Model Under Test.
|
use work.ctrl_pkg.all;
|
use work.ctrl_pkg.all;
|
| Line 76... |
Line 122... |
use work.eppwbn_pkg.all;
|
use work.eppwbn_pkg.all;
|
|
|
entity stimulus is
|
entity stimulus is
|
port(
|
port(
|
-- ADC
|
-- ADC
|
adc_data_I: inout std_logic_vector (9 downto 0) := 0;
|
adc_data_I: inout std_logic_vector (9 downto 0) := (others => '0');
|
adc_sel_O: in std_logic;
|
adc_sel_O: in std_logic;
|
adc_clk_O: in std_logic;
|
adc_clk_O: in std_logic;
|
adc_sleep_O: in std_logic;
|
adc_sleep_O: in std_logic;
|
adc_chip_sel_O: in std_logic;
|
adc_chip_sel_O: in std_logic;
|
|
|
-- EPP
|
-- EPP
|
nStrobe_I: inout std_logic; -- HostClk/nWrite
|
nStrobe_I: inout std_logic; -- HostClk/nWrite
|
Data_IO: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)
|
Data_IO: inout std_logic_vector (7 downto 0);-- AD8..1 (Data1..Data8)
|
nAck_O: in std_logic; -- PtrClk/PeriphClk/Intr
|
nAck_O: in std_logic; -- PtrClk/PeriphClk/Intr
|
busy_O: in std_logic; -- PtrBusy/PeriphAck/nWait
|
Busy_O: in std_logic; -- PtrBusy/PeriphAck/nWait
|
PError_O: in std_logic; -- AckData/nAckReverse
|
PError_O: in std_logic; -- AckData/nAckReverse
|
Sel_O: in std_logic; -- XFlag (Select)
|
Sel_O: in std_logic; -- XFlag (Select)
|
nAutoFd_I: inout std_logic; -- HostBusy/HostAck/nDStrb
|
nAutoFd_I: inout std_logic; -- HostBusy/HostAck/nDStrb
|
PeriphLogicH_O: in std_logic; -- (Periph Logic High)
|
PeriphLogicH_O: in std_logic; -- (Periph Logic High)
|
nInit_I: inout std_logic; -- nReverseRequest
|
nInit_I: inout std_logic; -- nReverseRequest
|
nFault_O: in std_logic; -- nDataAvail/nPeriphRequest
|
nFault_O: in std_logic; -- nDataAvail/nPeriphRequest
|
nSelectIn_I: inout std_logic; -- 1284 Active/nAStrb
|
nSelectIn_I: inout std_logic; -- 1284 Active/nAStrb
|
|
|
-- Peripherals
|
-- Peripherals
|
reset_I: inout std_logic;
|
reset_I: inout std_logic;
|
pll_clk_I: inout std_logic -- clock signal go to pll, and is divided in two clocks
|
pll_clk_I: inout std_logic; -- clock signal go to pll, and is divided in two clocks
|
|
|
|
test_number: out integer range 0 to 20
|
);
|
);
|
|
|
end stimulus;
|
end stimulus;
|
|
|
architecture STIMULATOR of stimulus is
|
architecture STIMULATOR of stimulus is
|
|
-- PLL clocks
|
|
constant CLK_DAQ_PERIOD: time := 25 ns;
|
|
constant CLK_EPP_PERIOD: time := 100 ns;
|
|
|
-- Control Signal Declarations
|
-- Control Signal Declarations
|
signal tb_InitFlag : boolean := false;
|
signal tb_InitFlag : boolean := false;
|
signal tb_ParameterInitFlag : boolean := false;
|
signal tb_ParameterInitFlag : boolean := false;
|
signal i: std_logic;
|
signal i: std_logic;
|
|
signal runflag: std_logic;
|
|
|
-- Parm Declarations
|
-- Parm Declarations
|
signal clk_Duty : real := 0.0;
|
signal clk_Duty : real := 0.0;
|
signal clk_Period : time := 0 ns;
|
signal clk_Period : time := 0 ns;
|
|
|
| Line 121... |
Line 173... |
P_AssignParms : process
|
P_AssignParms : process
|
variable clk_Duty_real : real;
|
variable clk_Duty_real : real;
|
variable clk_Period_real : real;
|
variable clk_Period_real : real;
|
begin
|
begin
|
-- Basic parameters
|
-- Basic parameters
|
clk_Period_real := 20.0; --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
|
clk_Period_real := 40.0; --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
|
clk_Period <= clk_Period_real * 1 ns;
|
clk_Period <= clk_Period_real * 1 ns;
|
clk_Duty_real := 50.0;
|
clk_Duty_real := 50.0;
|
clk_Duty <= clk_Duty_real;
|
clk_Duty <= clk_Duty_real;
|
|
|
tb_ParameterInitFlag <= true;
|
tb_ParameterInitFlag <= true;
|
| Line 133... |
Line 185... |
wait;
|
wait;
|
end process;
|
end process;
|
|
|
|
|
--------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------
|
-- Clocks
|
-- Instantiation
|
-- Clock Instantiation
|
-- Clock Instantiation
|
tb_clk: entity work.tb_simple_clock
|
U_TB_CLK: entity work.tb_simple_clock
|
port map (
|
port map (
|
clk_Period => clk_Period,
|
clk_Period => clk_Period,
|
clk_Duty => clk_Duty,
|
clk_Duty => clk_Duty,
|
active => tb_InitFlag,
|
active => tb_InitFlag,
|
clk_o => pll_clk_I
|
clk_o => pll_clk_I
|
);
|
);
|
|
|
|
-- ADC Instantiation
|
|
U_TB_ADC: entity work.virtual_adc
|
|
port map(
|
|
clk_I => adc_clk_O,
|
|
sel_I => adc_sel_O,
|
|
chip_sel_I => adc_chip_sel_O,
|
|
sleep_I => adc_sleep_O,
|
|
data_O => adc_data_I
|
|
);
|
|
|
|
|
--------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------
|
-- Clocked Sequences
|
-- Main process
|
P_virtual_adc: process (adc_clk_O)
|
P_Unclocked : process
|
variable data1: std_logic_vector(9 downto 0) := 1; -- odd
|
------------------------------------------------------------------------------------------------
|
variable data2: std_logic_vector(9 downto 0) := 0; -- pair
|
-- Procedure for write in epp port
|
|
procedure WriteData(
|
|
constant in_address: in std_logic_vector(7 downto 0);
|
|
constant in_data: in std_logic_vector(15 downto 0);
|
|
signal Data_IO: out std_logic_vector(7 downto 0);
|
|
signal nStrobe_I: out std_logic;
|
|
signal nSelectIn_I: out std_logic;
|
|
signal nAutoFd_I: out std_logic;
|
|
signal Busy_O: in std_logic
|
|
) is
|
begin
|
begin
|
if adc_clk_O'event and adc_clk_O = '1' then
|
nStrobe_I <= '0'; -- '0' -> is write
|
data1 <= data1 + 2;
|
|
data2 <= data2 + 2;
|
|
end if;
|
|
|
|
|
Data_IO <= in_address; -- Address
|
|
nSelectIn_I <= '0'; -- addStb
|
|
wait until Busy_O = '1';
|
|
--wait for 30 ns;
|
|
nSelectIn_I <= '1';
|
|
wait until Busy_O = '0';
|
|
|
|
Data_IO <= in_data(7 downto 0); -- Data1
|
|
nAutoFd_I <= '0'; -- datStb
|
|
wait until Busy_O = '1';
|
|
nAutoFd_I <= '1';
|
|
wait until Busy_O = '0';
|
|
|
|
Data_IO <= in_data(15 downto 8); -- Data0
|
|
nAutoFd_I <= '0'; -- datStb
|
|
wait until Busy_O = '1';
|
|
nAutoFd_I <= '1';
|
|
wait until Busy_O = '0';
|
|
|
|
end procedure WriteData;
|
|
------------------------------------------------------------------------------------------------
|
|
-- Procedure for read from epp port
|
|
procedure ReadData(
|
|
signal out_runflag: out std_logic;
|
|
constant in_address: in std_logic_vector(7 downto 0);
|
|
signal Data_IO: inout std_logic_vector(7 downto 0);
|
|
signal nStrobe_I: out std_logic;
|
|
signal nSelectIn_I: out std_logic;
|
|
signal nAutoFd_I: out std_logic;
|
|
signal Busy_O: in std_logic
|
|
) is
|
|
begin
|
|
|
case adc_sel_O is
|
nStrobe_I <= '0'; -- '0' -> is write
|
when '0' =>
|
Data_IO <= in_address; -- Address
|
adc_data_I <= data1;
|
nSelectIn_I <= '0'; -- addStb
|
when others =>
|
wait until Busy_O = '1';
|
adc_data_I <= data2;
|
--wait for 30 ns;
|
end case;
|
nSelectIn_I <= '1';
|
end process;
|
wait until Busy_O = '0';
|
|
|
|
nStrobe_I <= '1'; -- '1' -> is read
|
|
Data_IO <= (others => 'Z'); -- Data1
|
|
nAutoFd_I <= '0'; -- datStb
|
|
wait until (Busy_O = '1');
|
|
wait for 30 ns;
|
|
nAutoFd_I <= '1';
|
|
wait until (Busy_O = '0');
|
|
|
|
Data_IO <= (others => 'Z'); -- Data0
|
|
nAutoFd_I <= '0'; -- datStb
|
|
wait until (Busy_O = '1');
|
|
wait for 30 ns;
|
|
out_runflag <= Data_IO(6);
|
|
nAutoFd_I <= '1';
|
|
wait until (Busy_O = '0');
|
|
|
--------------------------------------------------------------------------------------------------
|
end procedure ReadData;
|
-- Sequence: Unclocked
|
|
P_Unclocked : process
|
|
|
|
begin
|
begin
|
|
------------------------------------------------------------------------------------------------
|
|
-- Init
|
|
test_number <= 0;
|
wait until tb_ParameterInitFlag;
|
wait until tb_ParameterInitFlag;
|
tb_InitFlag <= true;
|
tb_InitFlag <= true;
|
|
|
load_I <= '0';
|
nSelectIn_I <= '0';
|
RST_I <= '1';
|
nStrobe_I <= '0';
|
STB_I_port <= '1';
|
Data_IO <= (others => '0');
|
CYC_I_port <= '1';
|
nAutoFd_I <= '1';
|
WE_I_port <= '0';
|
nInit_I <= '1';
|
initial_address_I <= B"01_0000_0000_0000";
|
reset_I <= '1';
|
biggest_address_I <= B"11_1100_0000_0000";
|
wait for 700 ns; -- PLL delay
|
pause_address_I <= B"00_0000_1000_0000";
|
|
enable_I <= '1';
|
reset_I <= '0';
|
wait for 1.5 * clk_Period;
|
|
|
-- EPP Mode Negotiation
|
RST_I <= '0';
|
-- Standar timing and handshake
|
wait for 1.0 * clk_Period;
|
nStrobe_I <= '1';
|
|
wait for 500 ns;
|
load_I <= '1';
|
|
wait for 1.0 * clk_Period;
|
Data_IO <= X"40";
|
|
wait for 500 ns;
|
|
|
|
nSelectIn_I <= '1';
|
|
nAutoFd_I <= '0';
|
|
wait until (PError_O = '1' and nAck_O = '0' and nFault_O = '1' and Sel_O = '1');
|
|
|
|
nStrobe_I <= '0';
|
|
wait for 500 ns;
|
|
|
|
nAutoFd_I <= '1';
|
|
nStrobe_I <= '1';
|
|
wait until (nAck_O = '1' and Sel_O = '1');
|
|
|
|
------------------------------------------------------------------------------------------------
|
|
-- Test 1
|
|
-- Writing in all control register
|
|
|
|
-- 00 RunConf_R RW [ | | | | |TScal04|TScal03|TScal02|
|
|
-- TScal01|TScal00|TScalEn| TrCh| TrEdg| TrOn| Cont| Start]
|
|
--
|
|
-- 01 Channels_R RW [ | | | | | | | |
|
|
-- | | | | | | RCh01| RCh00]
|
|
--
|
|
-- 02 BuffSize_R RW [ | |BuffS13|BuffS12|BuffS11|BuffS10|BuffS09|BuffS08|
|
|
-- BuffS07|BuffS06|BuffS05|BuffS04|BuffS03|BuffS02|BuffS01|BuffS00]
|
|
--
|
|
-- 03 TrigLvl_R RW [ | | | | | |TrLvl09|TrLvl08|
|
|
-- TrLvl07|TrLvl06|TrLvl05|TrLvl04|TrLvl03|TrLvl02|TrLvl01|TrLvl00]
|
|
--
|
|
-- 04 TrigOff_R RW [ |TrOff14|TrOff13|TrOff12|TrOff11|TrOff10|TrOff09|TrOff08|
|
|
-- TrOff07|TrOff06|TrOff00|TrOff00|TrOff00|TrOff00|TrOff00|TrOff00]
|
|
--
|
|
-- 05 ADCConf RW [ | | | | ADCS|ADSleep| ADPSEn| ADPS08|
|
|
-- ADPS07| ADPS06| ADPS05| ADPS04| ADPS03| ADPS02| ADPS01| ADPS00]
|
|
--
|
|
-- 08 Data_O R [ErrFlag|RunFlag| | | | DCh00| Dat09| Dat08|
|
|
-- Dat07| Dat06| Dat05| Dat04| Dat03| Dat02| Dat01| Dat00]
|
|
--
|
|
-- 09 Error_O R [ | | | | | | | |
|
|
-- | | | | | ErrN02| ErrN01| ErrN00]
|
|
test_number <= 1;
|
|
|
|
WriteData(X"00", X"FFFE", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
|
|
WriteData(X"01", X"FFFF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
|
|
WriteData(X"02", X"FFFF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
|
|
WriteData(X"03", X"FFFF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
|
|
WriteData(X"04", X"FFFF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
|
|
|
|
ReadData(runflag, X"00", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
|
|
ReadData(runflag,X"01", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
|
|
ReadData(runflag, X"02", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
|
|
ReadData(runflag, X"03", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
|
|
ReadData(runflag, X"04", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
|
|
|
|
wait for 50 ns;
|
|
------------------------------------------------------------------------------------------------
|
|
-- Test 2 - DAQ Config
|
|
-- Writing in daq config register
|
|
test_number <= 2;
|
|
|
|
WriteData(X"05", X"07FF", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
|
|
ReadData(runflag, X"05", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
|
|
|
|
WriteData(X"05", X"0A00", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
|
|
ReadData(runflag, X"05", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
|
|
|
|
wait for 50 ns;
|
|
------------------------------------------------------------------------------------------------
|
|
-- Test 3 - Test basic
|
|
-- daq freq = ctrl freq/2 (default), w/o trigger, w/o skipper, channels 1 and 2,
|
|
-- buffer size = 50h, continuous
|
|
test_number <= 3;
|
|
|
|
WriteData(X"01", X"0003", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- Channels_R
|
|
WriteData(X"02", X"0050", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- BuffSize_R
|
|
WriteData(X"03", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigLvl_R
|
|
WriteData(X"04", X"0000", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- TrigOff_R
|
|
WriteData(X"00", X"0001", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O); -- RunConf_R
|
|
|
|
|
|
ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
|
|
while (runflag = '1') loop
|
|
ReadData(runflag, X"08", Data_IO, nStrobe_I, nSelectIn_I, nAutoFd_I, Busy_O);
|
|
end loop;
|
|
|
|
wait for 50 ns;
|
|
------------------------------------------------------------------------------------------------
|
|
-- Test 4 - Skipper
|
|
-- daq freq = ctrl freq/2 (default), w/o trigger, skipper = 3, channels 1 and 2,
|
|
-- buffer size = 80, no continuous
|
|
|
load_I <= '0';
|
|
wait until ADR_O_mem = B"00_0000_1000_0000";
|
|
wait for 8.0 * clk_Period;
|
|
|
|
pause_address_I <= B"01_0000_0000_0000";
|
------------------------------------------------------------------------------------------------
|
wait for 20.0 * clk_Period;
|
-- Test 5 - Trigger - one shot
|
|
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, not continuous, skipper = 5,
|
|
-- channels 1 and 2, buffer size = 100
|
|
|
enable_I <= '0';
|
|
wait for 8.0 * clk_Period;
|
|
|
|
enable_I <= '1';
|
------------------------------------------------------------------------------------------------
|
|
-- Test 6 - Trigger
|
|
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, continuous, skipper = 5,
|
|
-- channels 1, buffer size = 50
|
|
|
|
|
wait until finish_O = '1';
|
------------------------------------------------------------------------------------------------
|
wait for 2.0 * clk_Period;
|
-- Test 7 - One channel
|
|
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, continuous, skipper = 5,
|
|
-- channels 1, buffer size = 50
|
|
|
tb_InitFlag <= false;
|
|
wait;
|
|
|
|
|
|
end process;
|
------------------------------------------------------------------------------------------------
|
|
-- Test 8 - Test write while working
|
|
-- daq freq = ctrl freq/2 (default), trigger channel 1, level 30 %, continuous, skipper = 5,
|
|
-- channels 1, buffer size = 50
|
|
|
|
|
|
|
--------------------------------------------------------------------------------------------------
|
|
-- Conditional signals
|
|
|
|
P_mem: process(STB_O_mem, DAT_I_mem, CYC_O_mem, CLK_I, RST_I,i)
|
wait for 100 ns;
|
|
|
begin
|
tb_InitFlag <= false;
|
if STB_O_mem = '1' and CYC_O_mem = '1' and i = '1' then
|
wait;
|
ACK_I_mem <= '1';
|
|
else
|
|
ACK_I_mem <= '0';
|
|
end if;
|
|
|
|
if CLK_I'event and CLK_I = '1' then
|
|
if RST_I = '1' then
|
|
DAT_I_mem <= (others => '0');
|
|
elsif STB_O_mem = '1' and CYC_O_mem = '1' and i = '1' then
|
|
DAT_I_mem <= DAT_I_mem + 1;
|
|
end if;
|
|
end if;
|
|
|
|
if CLK_I'event and CLK_I = '1' then
|
|
if RST_I = '1' then
|
|
i <= '0';
|
|
elsif STB_O_mem = '1' and CYC_O_mem = '1' then
|
|
i <= not(i);
|
|
end if;
|
|
end if;
|
|
|
|
end process;
|
end process;
|
|
|
|
|
|
|
| Line 264... |
Line 449... |
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
|
-->>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
|
library ieee, std;
|
library ieee, std;
|
use ieee.std_logic_1164.all;
|
use ieee.std_logic_1164.all;
|
|
|
|
|
|
|
-- Additional libraries used by Model Under Test.
|
-- Additional libraries used by Model Under Test.
|
-- ...
|
-- ...
|
|
|
entity testbench is
|
entity testbench is
|
generic (
|
|
MEM_ADD_WIDTH: integer := 14
|
|
);
|
|
end testbench;
|
end testbench;
|
|
|
architecture tbGeneratedCode of testbench is
|
architecture tbGeneratedCode of testbench is
|
-- ADC
|
-- ADC
|
signal adc_data_I: std_logic_vector (9 downto 0);
|
signal adc_data_I: std_logic_vector (9 downto 0);
|
| Line 296... |
Line 476... |
signal nFault_O: std_logic;
|
signal nFault_O: std_logic;
|
signal nSelectIn_I: std_logic;
|
signal nSelectIn_I: std_logic;
|
-- Peripherals
|
-- Peripherals
|
signal reset_I: std_logic;
|
signal reset_I: std_logic;
|
signal pll_clk_I: std_logic;
|
signal pll_clk_I: std_logic;
|
|
|
|
|
|
signal test_number: integer range 0 to 20;
|
begin
|
begin
|
--------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------
|
-- Instantiation of Stimulus.
|
-- Instantiation of Stimulus.
|
U_stimulus_0 : entity work.stimulus
|
U_stimulus_0 : entity work.stimulus
|
generic map (
|
|
MEM_ADD_WIDTH=> MEM_ADD_WIDTH
|
|
)
|
|
port map (
|
port map (
|
-- ADC
|
-- ADC
|
adc_data_I => adc_data_I,
|
adc_data_I => adc_data_I,
|
adc_sel_O => adc_sel_O,
|
adc_sel_O => adc_sel_O,
|
adc_clk_O => adc_clk_O,
|
adc_clk_O => adc_clk_O,
|
| Line 324... |
Line 504... |
nInit_I => nInit_I,
|
nInit_I => nInit_I,
|
nFault_O => nFault_O,
|
nFault_O => nFault_O,
|
nSelectIn_I => nSelectIn_I,
|
nSelectIn_I => nSelectIn_I,
|
-- Peripherals
|
-- Peripherals
|
reset_I => reset_I,
|
reset_I => reset_I,
|
pll_clk_I => pll_clk_I
|
pll_clk_I => pll_clk_I,
|
|
|
|
test_number => test_number
|
);
|
);
|
|
|
--------------------------------------------------------------------------------------------------
|
--------------------------------------------------------------------------------------------------
|
-- Instantiation of Model Under Test.
|
-- Instantiation of Model Under Test.
|
U_outman_0 : entity work.modular_oscilloscope --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
|
U_OSC0 : entity work.modular_oscilloscope --<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--<--
|
generic map (
|
|
MEM_ADD_WIDTH=> MEM_ADD_WIDTH
|
|
)
|
|
port map (
|
port map (
|
-- ADC
|
-- ADC
|
adc_data_I => adc_data_I,
|
adc_data_I => adc_data_I,
|
adc_sel_O => adc_sel_O,
|
adc_sel_O => adc_sel_O,
|
adc_clk_O => adc_clk_O,
|
adc_clk_O => adc_clk_O,
|
