URL
https://opencores.org/ocsvn/myblaze/myblaze/trunk
[/] [myblaze/] [trunk/] [rtl/] [dsram.py] - Diff between revs 5 and 6
Show entire file |
Details |
Blame |
View Log
| Rev 5 |
Rev 6 |
| Line 6... |
Line 6... |
Dual port synchronous ram
|
Dual port synchronous ram
|
|
|
:copyright: Copyright (c) 2010 Jian Luo
|
:copyright: Copyright (c) 2010 Jian Luo
|
:author-email: jian.luo.cn(at_)gmail.com
|
:author-email: jian.luo.cn(at_)gmail.com
|
:license: LGPL, see LICENSE for details
|
:license: LGPL, see LICENSE for details
|
:revision: $Id: dsram.py 5 2010-11-21 10:59:30Z rockee $
|
:revision: $Id: dsram.py 6 2010-11-21 23:18:44Z rockee $
|
"""
|
"""
|
|
|
from myhdl import *
|
from myhdl import *
|
from defines import *
|
from defines import *
|
from functions import *
|
from functions import *
|
| Line 19... |
Line 19... |
width=32, size=8):
|
width=32, size=8):
|
"""
|
"""
|
Dual port synchronous RAM with New Data Read-During-Write Behavior
|
Dual port synchronous RAM with New Data Read-During-Write Behavior
|
"""
|
"""
|
ram = [Signal(intbv(0)[width:]) for i in range(2**size)]
|
ram = [Signal(intbv(0)[width:]) for i in range(2**size)]
|
#read_addr = Signal(intbv(0)[len(adr_i):])
|
|
@always(clock.posedge)
|
@always(clock.posedge)
|
def logic():
|
def logic():
|
if ena_i:
|
if ena_i:
|
if wre_i:
|
if wre_i:
|
ram[int(adr_w_i)].next = dat_w_i
|
ram[int(adr_w_i)].next = dat_w_i
|
dat_o.next = ram[int(adr_i)]
|
dat_o.next = ram[int(adr_i)]
|
#read_addr.next = adr_i
|
|
# XXX: Hacked to assure read after write
|
|
#if adr_w_i == adr_i:
|
|
#dat_o.next = dat_w_i
|
|
#else:
|
|
#dat_o.next = ram[int(adr_i)]
|
|
#else:
|
|
#dat_o.next = ram[int(adr_i)]
|
|
#@always_comb
|
|
#def passthrough():
|
|
#dat_o.next = ram[int(read_addr)]
|
|
|
|
return instances()
|
return instances()
|
|
|
### EOF ###
|
### EOF ###
|
# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
|
# vim:smarttab:sts=4:ts=4:sw=4:et:ai:tw=80:
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.