| Line 61... |
Line 61... |
constant ldram: integer := blocksizeld + ldways - 1;
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constant ldram: integer := blocksizeld + ldways - 1;
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constant ldqueuelength: integer := ldram;
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constant ldqueuelength: integer := ldram;
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type IOType is ( Start, busy);
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type IOType is ( Start, busy);
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type tType is ( inittag, startt, startt1, tagtest, tagwait, stateget, stateget1, finish, finished);
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type tType is ( inittag, startt, startt1, tagtest, tagwait, stateget, stateget1, finish, finished);
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type rType is ( raminit, ramstart, ramstart1, ramcheck, ramcheck1, ramcheck2, ramread, ramread1, ramupdate,
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type rType is ( raminit, ramstart, ramstart1, ramread, ramread1, ramupdate,
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ramupdate1, ramupdate2, ramupdate3, ramflush, ramflush1, ramwait, ramwait1, ramclean, ramclean1);
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ramupdate1, ramupdate2, ramupdate3, ramflush, ramflush1, ramwait, ramwait1, ramclean, ramclean1);
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type fType is ( queuestart, queuewait, queuewaitAm1, queuewaitAm2, queuewaitA11, queuewaitA12, queueelim);
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type fType is ( queuestart, queuewait, queuewaitAm1, queuewaitAm2, queuewaitA11, queuewaitA12, queueelim);
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subtype myint is natural range 15 downto 0;
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subtype myint is natural range 15 downto 0;
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type TagRAMType is record
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type TagRAMType is record
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cacheAddr: std_ulogic_vector( ldram - 1 downto 0);
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cacheAddr: std_ulogic_vector( ldram - 1 downto 0);
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| Line 137... |
Line 137... |
signal statetag: tType;
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signal statetag: tType;
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signal stateram: rType;
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signal stateram: rType;
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signal statequeue: fType;
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signal statequeue: fType;
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signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted,
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signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted,
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interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt, serviced, oldint: std_ulogic;
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interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt, serviced, oldint: std_ulogic;
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signal gal: std_ulogic_vector( 7 downto 0);
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begin
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begin
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| Line 210... |
Line 211... |
done <= '0'; -- NEW
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done <= '0'; -- NEW
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initcount <= ( others => '0');
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initcount <= ( others => '0');
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AddressInt <= ( others => '0');
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AddressInt <= ( others => '0');
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IOCodeh <= ( others => '0');
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IOCodeh <= ( others => '0');
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AddressInh <= ( others => '0');
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AddressInh <= ( others => '0');
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gal <= ( others => '1');
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else
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else
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gal <= gal( 6 downto 4) & ( gal( 3) xor gal( 7)) & ( gal( 2) xor gal( 7)) & ( gal( 1) xor gal( 7)) & gal( 0) & gal( 7);
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oldint <= interrupt;
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oldint <= interrupt;
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case statetag is
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case statetag is
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when inittag =>
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when inittag =>
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for i in tagRAMIn'range loop
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for i in tagRAMIn'range loop
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tagRAMIn(i).tagValid <= '0';
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tagRAMIn(i).tagValid <= '0';
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| Line 257... |
Line 259... |
end loop;
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end loop;
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found <= a;
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found <= a;
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free <= b;
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free <= b;
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if ways = 1 then
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elim <= 0;
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else
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elim <= to_integer( gal( ways - 1 downto 0));
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end if;
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if stateram = ramstart then
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if stateram = ramstart then
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enableram <= '1';
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enableram <= '1';
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statetag <= tagwait;
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statetag <= tagwait;
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end if;
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end if;
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when tagwait =>
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when tagwait =>
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| Line 344... |
Line 352... |
writeb <= '0';
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writeb <= '0';
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readb <= '0';
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readb <= '0';
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getf <= '0';
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getf <= '0';
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putf <= '0'; -- NEW inserted
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putf <= '0'; -- NEW inserted
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doneh <= '0';
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doneh <= '0';
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elim <= 15;
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accinterrupt <= '0';
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accinterrupt <= '0';
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accqueue <= '0';
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accqueue <= '0';
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initcount1 <= ( others => '0');
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initcount1 <= ( others => '0');
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FreeIn <= ( others => '0');
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FreeIn <= ( others => '0');
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firstf <= ( others => '0');
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firstf <= ( others => '0');
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| Line 389... |
Line 396... |
stateram <= ramupdate;
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stateram <= ramupdate;
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elsif free /= 15 then
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elsif free /= 15 then
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en := '1';
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en := '1';
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stateram <= ramwait;
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stateram <= ramwait;
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else
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else
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elim <= 0;
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stateram <= ramcheck;
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end if;
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end if;
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when ramcheck =>
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cindex <= tagBuff( elim).cacheAddr;
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cindex <= tagBuff( elim).cacheAddr;
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stateram <= ramcheck1;
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stateram <= ramupdate;
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when ramcheck1 =>
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end if;
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stateram <= ramcheck2;
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when ramcheck2 =>
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if cacheOut.Am = '0' or elim = ways - 1 then
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RecBuff <= cacheOut;
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en := '1';
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stateram <= ramwait;
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else
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elim <= elim + 1;
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stateram <= ramcheck;
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end if;
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end if;
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when ramupdate =>
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when ramupdate =>
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stateram <= ramupdate1;
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stateram <= ramupdate1;
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when ramupdate1 =>
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when ramupdate1 =>
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cacheIn <= cacheOut;
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cacheIn <= cacheOut;
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