| Line 135... |
Line 135... |
signal found, free, elim, del: myint;
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signal found, free, elim, del: myint;
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signal stateIO: IOType;
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signal stateIO: IOType;
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signal statetag: tType;
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signal statetag: tType;
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signal stateram: rType;
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signal stateram: rType;
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signal statequeue: fType;
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signal statequeue: fType;
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signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted, isfull, flag,
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signal enableram, enablequeue, queuedone, readsh, writesh, doneh, preempted, isfull, flag, flag1,
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interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt, serviced, oldint: std_ulogic;
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interrupt, readb, writeb, writec, writet, accdone, accqueue, accinterrupt, serviced, oldint: std_ulogic;
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signal gal: std_ulogic_vector( 7 downto 0);
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signal gal: std_ulogic_vector( 7 downto 0);
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begin
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begin
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| Line 356... |
Line 356... |
doneh <= '0';
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doneh <= '0';
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accinterrupt <= '0';
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accinterrupt <= '0';
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accqueue <= '0';
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accqueue <= '0';
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isfull <= '0';
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isfull <= '0';
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flag <= '0';
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flag <= '0';
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flag1 <= '1';
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initcount1 <= ( others => '0');
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initcount1 <= ( others => '0');
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FreeIn <= ( others => '0');
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FreeIn <= ( others => '0');
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firstf <= ( others => '0');
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firstf <= ( others => '0');
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lastf <= ( others => '0');
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lastf <= ( others => '0');
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counterf <= ( others => '0');
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counterf <= ( others => '0');
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| Line 389... |
Line 390... |
if enableram = '1' then -- UPDATE
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if enableram = '1' then -- UPDATE
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if isfull = '0' then
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if isfull = '0' then
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tagBuff <= tagRAMOut;
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tagBuff <= tagRAMOut;
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end if;
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end if;
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if found /= 15 then
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if found /= 15 then
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tagBuff <= tagRAMOut;
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cindex <= tagRAMOut( found).cacheAddr;
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cindex <= tagRAMOut( found).cacheAddr;
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isfull <= '0';
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isfull <= '0';
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stateram <= ramupdate;
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stateram <= ramupdate;
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elsif free /= 15 then
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elsif free /= 15 then
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en := '1';
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en := '1';
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if emptyf = '1' and isfull = '0' then
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if emptyf = '1' and isfull = '0' then
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isfull <= '1';
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isfull <= '1';
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tagBuff <= tagRAMOut;
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stateram <= ramwait;
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stateram <= ramwait;
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else
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else
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cindex <= FreeOut;
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cindex <= FreeOut;
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if isfull = '1' then
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if isfull = '1' then
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tagBuff( free).cacheAddr <= FreeOut;
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tagBuff( free).cacheAddr <= FreeOut;
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| Line 409... |
Line 412... |
else
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else
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tagRAMOut( free).cacheAddr <= FreeOut;
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tagRAMOut( free).cacheAddr <= FreeOut;
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tagRAMOut( free).cacheValid <= '1';
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tagRAMOut( free).cacheValid <= '1';
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tagRAMOut( free).tag <= AddressInh( tagRAMOut( free).tag'range);
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tagRAMOut( free).tag <= AddressInh( tagRAMOut( free).tag'range);
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tagRAMOut( free).tagValid <= '1';
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tagRAMOut( free).tagValid <= '1';
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flag1 <= '1';
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end if;
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end if;
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isfull <= '0';
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isfull <= '0';
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getf <= '1';
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getf <= '1';
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if IOCodeh = "111" and ldCachedWords = 0 then
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if IOCodeh = "111" and ldCachedWords = 0 then
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stateram <= ramupdate2;
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stateram <= ramupdate2;
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| Line 463... |
Line 467... |
stateram <= ramclean;
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stateram <= ramclean;
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end if;
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end if;
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when ramread =>
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when ramread =>
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readb <= '0';
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readb <= '0';
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getf <= '0';
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getf <= '0';
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if flag1 = '1' then
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tagBuff <= tagRAMOut;
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flag1 <= '0';
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end if;
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stateram <= ramread1;
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stateram <= ramread1;
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when ramread1 =>
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when ramread1 =>
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if readsh = '0' then
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if readsh = '0' then
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for i in blockIn'range loop
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for i in blockIn'range loop
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cacheIn.Words( i) <= blockIn( i);
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cacheIn.Words( i) <= blockIn( i);
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end loop;
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end loop;
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stateram <= ramupdate2;
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stateram <= ramupdate2;
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end if;
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end if;
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when ramupdate2 =>
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when ramupdate2 =>
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if flag1 = '1' then
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tagBuff <= tagRAMOut;
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flag1 <= '0';
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end if;
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if IOCodeh(2) = '1' then
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if IOCodeh(2) = '1' then
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if IOCodeh(1) = '1' then
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if IOCodeh(1) = '1' then
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If IOCodeh(0) = '1' then
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If IOCodeh(0) = '1' then
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cacheIn.Words( index).Word <= DataInh;
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cacheIn.Words( index).Word <= DataInh;
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cacheIn.Words( index).Modified <= "1111";
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cacheIn.Words( index).Modified <= "1111";
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