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Line 33... |
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Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.
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Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.
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Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions
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Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions
|
are executed. Whenever an unexpected situation occurs the application code is informed via precise and resumable hardware exceptions.
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are executed. Whenever an unexpected situation occurs the application code is informed via precise and resumable hardware exceptions.
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|
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:thinking: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale).
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:interrobang: Want to know more? Check out the [project's rationale](https://stnolting.github.io/neorv32/#_rationale).
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|
|
:books: For detailed information take a look at the [NEORV32 documentation](https://stnolting.github.io/neorv32/) (online at GitHub-pages).
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:books: For detailed information take a look at the [NEORV32 documentation](https://stnolting.github.io/neorv32/) (online at GitHub-pages).
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|
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:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
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:label: The project's change log is available in [`CHANGELOG.md`](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md).
|
To see the changes between _official releases_ visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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To see the changes between _official releases_ visit the project's [release page](https://github.com/stnolting/neorv32/releases).
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| Line 57... |
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setting up your NEORV32 setup!
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setting up your NEORV32 setup!
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### Project Key Features
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### Project Key Features
|
|
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- [x] all-in-one package: [CPU](#3-NEORV32-CPU-Features) plus [SoC](#2-NEORV32-Processor-Features) plus [Software Framework & Tooling](#4-Software-Framework-and-Tooling)
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- [x] all-in-one package: **CPU** plus **SoC** plus **Software Framework & Tooling**
|
- [x] completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
|
- [x] completely described in behavioral, platform-independent VHDL - no primitives, macros, etc.
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- [x] be as small as possible while being as RISC-V-compliant as possible
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- [x] be as small as possible while being as RISC-V-compliant as possible
|
- [x] from zero to *printf("hello world!");* - completely open source and documented
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- [x] from zero to `printf("hello world!");` - completely open source and documented
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- [x] easy to use even for FPGA/RISC-V starters – intended to work *out of the box*
|
- [x] easy to use even for FPGA/RISC-V starters – intended to work *out of the box*
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### Status
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### Status
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| Line 80... |
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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## 2. NEORV32 Processor Features
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## 2. NEORV32 Processor Features
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|
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The NEORV32 Processor (top entity: [`rtl/core/neorv32_top.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_top.vhd))
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The NEORV32 Processor provides a full-featured microcontroller-like SoC build around the NEORV32 CPU. It is highly configurable
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provides a full-featured SoC build around the NEORV32 CPU. It is highly configurable via generics
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via generics to allow a flexible customization according to your needs. Note that all modules listed below are _optional_.
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to allow a flexible customization according to your needs. Note that all modules listed below are _optional_.
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**Memory**
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**Memory**
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* processor-internal data and instruction memories ([DMEM](https://stnolting.github.io/neorv32/#_data_memory_dmem) /
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* processor-internal data and instruction memories ([DMEM](https://stnolting.github.io/neorv32/#_data_memory_dmem) /
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[IMEM](https://stnolting.github.io/neorv32/#_instruction_memory_imem)) &
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[IMEM](https://stnolting.github.io/neorv32/#_instruction_memory_imem)) &
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cache ([iCACHE](https://stnolting.github.io/neorv32/#_processor_internal_instruction_cache_icache))
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cache ([iCACHE](https://stnolting.github.io/neorv32/#_processor_internal_instruction_cache_icache))
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* bootloader ([BOOTLDROM](https://stnolting.github.io/neorv32/#_bootloader_rom_bootrom)) with serial user interface
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* pre-installed bootloader ([BOOTLDROM](https://stnolting.github.io/neorv32/#_bootloader_rom_bootrom)) with serial user interface
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* allows booting application code via UART or from external SPI flash
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* allows booting application code via UART or from external SPI flash
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**Timers**
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**Timers**
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|
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* machine system timer, 64-bit ([MTIME](https://stnolting.github.io/neorv32/#_machine_system_timer_mtime)), RISC-V spec. compatible
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* machine system timer, 64-bit ([MTIME](https://stnolting.github.io/neorv32/#_machine_system_timer_mtime)), RISC-V spec. compatible
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| Line 103... |
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**Input/Output**
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**Input/Output**
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* standard serial interfaces
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* standard serial interfaces
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([UART](https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0),
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([UART](https://stnolting.github.io/neorv32/#_primary_universal_asynchronous_receiver_and_transmitter_uart0),
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[SPI](https://stnolting.github.io/neorv32/#_serial_peripheral_interface_controller_spi),
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[SPI](https://stnolting.github.io/neorv32/#_serial_peripheral_interface_controller_spi),
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[TWI / I²C](https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi))
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[TWI](https://stnolting.github.io/neorv32/#_two_wire_serial_interface_controller_twi))
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* general purpose [GPIO](https://stnolting.github.io/neorv32/#_general_purpose_input_and_output_port_gpio) and
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* general purpose [GPIO](https://stnolting.github.io/neorv32/#_general_purpose_input_and_output_port_gpio) and
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[PWM](https://stnolting.github.io/neorv32/#_pulse_width_modulation_controller_pwm)
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[PWM](https://stnolting.github.io/neorv32/#_pulse_width_modulation_controller_pwm)
|
* smart LED interface ([NEOLED](https://stnolting.github.io/neorv32/#_smart_led_interface_neoled)) to directly drive _NeoPixel(TM)_ LEDs
|
* smart LED interface ([NEOLED](https://stnolting.github.io/neorv32/#_smart_led_interface_neoled)) to directly control NeoPixel(TM) LEDs
|
|
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**SoC Connectivity**
|
**SoC Connectivity**
|
|
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* 32-bit external bus interface, Wishbone b4 compatible
|
* 32-bit external bus interface, Wishbone b4 compatible
|
([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
|
([WISHBONE](https://stnolting.github.io/neorv32/#_processor_external_memory_interface_wishbone_axi4_lite))
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| Line 119... |
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* 32-bit stream link interface with up to 8 independent RX and TX links
|
* 32-bit stream link interface with up to 8 independent RX and TX links
|
([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink))
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([SLINK](https://stnolting.github.io/neorv32/#_stream_link_interface_slink))
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* AXI4-Stream compatible
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* AXI4-Stream compatible
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* external interrupt controller with up to 32 channels
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* external interrupt controller with up to 32 channels
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([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
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([XIRQ](https://stnolting.github.io/neorv32/#_external_interrupt_controller_xirq))
|
* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
|
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for tightly-coupled custom co-processor extensions
|
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**Advanced**
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**Advanced**
|
|
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* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
|
|
* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) accessible via JTAG interface - implementing
|
* on-chip debugger ([OCD](https://stnolting.github.io/neorv32/#_on_chip_debugger_ocd)) accessible via JTAG interface - implementing
|
the [*Minimal RISC-V Debug Specification Version 0.13.2*](https://github.com/riscv/riscv-debug-spec)
|
the "Minimal RISC-V Debug Specification Version 0.13.2" and compatible with **OpenOCD** + **gdb** and **Segger Embedded Studio**
|
and compatible with *OpenOCD* and *gdb*
|
* _true random_ number generator ([TRNG](https://stnolting.github.io/neorv32/#_true_random_number_generator_trng))
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* bus keeper to monitor the CPU's bus transactions ([BUSKEEPER](https://stnolting.github.io/neorv32/#_internal_bus_monitor_buskeeper))
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* execute in place module ([XIP](https://stnolting.github.io/neorv32/#_execute_in_place_module_xip)) to directly execute code from SPI flash
|
|
* custom functions subsystem ([CFS](https://stnolting.github.io/neorv32/#_custom_functions_subsystem_cfs))
|
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for tightly-coupled custom co-processor extensions and interfaces
|
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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[[back to top](#The-NEORV32-RISC-V-Processor)]
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|
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|
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### FPGA Implementation Results - Processor
|
### FPGA Implementation Results - Processor
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| Line 152... |
Line 150... |
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## 3. NEORV32 CPU Features
|
## 3. NEORV32 CPU Features
|
|
|
The CPU (top entity: [`rtl/core/neorv32_cpu.vhd`](https://github.com/stnolting/neorv32/blob/master/rtl/core/neorv32_cpu.vhd))
|
The NEORV32 CPU implements the RISC-V 32-bit `rv32i` ISA with optional extensions (see below). It is compatible to subsets of the
|
implements the RISC-V 32-bit `rv32` ISA with optional extensions (see below). It is compatible to subsets of the
|
|
*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
|
*Unprivileged ISA Specification* [(Version 2.2)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-spec.pdf)
|
and the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
|
and the *Privileged Architecture Specification* [(Version 1.12-draft)](https://github.com/stnolting/neorv32/blob/master/docs/references/riscv-privileged.pdf).
|
Compatibility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test)
|
Compatibility is checked by passing the [official RISC-V architecture tests](https://github.com/riscv/riscv-arch-test).
|
(see [`sim/README`](sim/README.md)).
|
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|
|
The core is a little-endian Von-Neumann machine implemented as multi-cycle architecture.
|
The core is a little-endian Von-Neumann machine implemented as multi-cycle architecture.
|
However, the CPU's _front end_ (instruction fetch) and _back end_ (instruction execution) can work independently to increase performance.
|
However, the CPU's _front end_ (instruction fetch) and _back end_ (instruction execution) can work independently to increase performance.
|
Currently, three privilege levels (`machine` and optional `user` and `debug_mode`) are supported. The CPU implements all three standard RISC-V machine
|
Currently, three privilege levels (`machine` and optional `user` and `debug_mode`) are supported. The CPU implements all three standard RISC-V machine
|
interrupts (`MTI`, `MEI`, `MSI`) plus 16 _fast interrupt requests_ as custom extensions.
|
interrupts (`MTI`, `MEI`, `MSI`) plus 16 _fast interrupt requests_ as custom extensions.
|
| Line 204... |
Line 200... |
### FPGA Implementation Results - CPU
|
### FPGA Implementation Results - CPU
|
|
|
Implementation results for _exemplary_ CPU configuration generated for an **Intel Cyclone IV EP4CE22F17C6N FPGA**
|
Implementation results for _exemplary_ CPU configuration generated for an **Intel Cyclone IV EP4CE22F17C6N FPGA**
|
using **Intel Quartus Prime Lite 20.1** ("balanced implementation, Slow 1200mV 0C Model").
|
using **Intel Quartus Prime Lite 20.1** ("balanced implementation, Slow 1200mV 0C Model").
|
|
|
| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)) | LEs | FFs | Memory bits | DSPs (9-bit) | f_max |
|
| CPU Configuration (version [1.5.7.10](https://github.com/stnolting/neorv32/blob/master/CHANGELOG.md)) | LEs | FFs | Memory bits | DSPs | f_max |
|
|:------------------------|:----:|:----:|:----:|:-:|:-------:|
|
|:------------------------|:----:|:----:|:----:|:-:|:-------:|
|
| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
|
| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz |
|
| `rv32i_Zicsr_Zicntr` | 1729 | 813 | 1024 | 0 | 124 MHz |
|
| `rv32i_Zicsr_Zicntr` | 1729 | 813 | 1024 | 0 | 124 MHz |
|
| `rv32imac_Zicsr_Zicntr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
|
| `rv32imac_Zicsr_Zicntr` | 2511 | 1074 | 1024 | 0 | 124 MHz |
|
|
|
:information_source: An incremental list of CPU extension's hardware utilization can found in the
|
:information_source: An incremental list of CPU extension's hardware utilization can found in the
|
[_Data Sheet: FPGA Implementation Results - CPU_](https://stnolting.github.io/neorv32/#_cpu).
|
[_Data Sheet: FPGA Implementation Results - CPU_](https://stnolting.github.io/neorv32/#_cpu).
|
|
|
:information_source: The CPU and SoC provide advanced options to optimize for performance, area or energy.
|
|
See [_User Guide: Application-Specific Processor Configuration_](https://stnolting.github.io/neorv32/ug/#_application_specific_processor_configuration)
|
|
for more information.
|
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
### Performance
|
### Performance
|
|
|
| Line 313... |
Line 305... |
* [Simulation](https://stnolting.github.io/neorv32/ug/#_simulating_the_processor) - simulate the whole SoC
|
* [Simulation](https://stnolting.github.io/neorv32/ug/#_simulating_the_processor) - simulate the whole SoC
|
* [Hello World!](https://stnolting.github.io/neorv32/ug/index.html#_hello_world) - run a quick _"hello world"_ simulation
|
* [Hello World!](https://stnolting.github.io/neorv32/ug/index.html#_hello_world) - run a quick _"hello world"_ simulation
|
|
|
### :copyright: Legal
|
### :copyright: Legal
|
|
|
[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
|
[](https://github.com/stnolting/neorv32/blob/master/LICENSE)
|
[](https://doi.org/10.5281/zenodo.5018888)
|
[](https://doi.org/10.5281/zenodo.5018888)
|
|
|
* [Overview](https://stnolting.github.io/neorv32/#_legal) - license, disclaimer, limitation of liability for external links, proprietary notice, ...
|
* [Overview](https://stnolting.github.io/neorv32/#_legal) - license, disclaimer, limitation of liability for external links, proprietary notice, ...
|
* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information
|
* [Citing](https://stnolting.github.io/neorv32/#_citing) - citing information
|
* [Impressum](https://github.com/stnolting/neorv32/blob/master/docs/impressum.md) - imprint
|
* [Impressum](https://github.com/stnolting/neorv32/blob/master/docs/impressum.md) - imprint
|
|
|
|
This is an open-source project that is free of charge. Use this project in any way you like
|
|
(as long as it complies to the permissive [license](https://github.com/stnolting/neorv32/blob/master/LICENSE)).
|
|
Please quote it appropriately. :+1:
|
|
|
|
We (the community) and I highly appreciate _any_ kind of feedback! Feel free to start a new "show & tell"
|
|
[discussion](https://github.com/stnolting/neorv32/discussions), write some lines on our [gitter channel](https://gitter.im/neorv32/community)
|
|
or directly get in [contact](mailto:stnolting@gmail.com) with me.
|
|
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
[[back to top](#The-NEORV32-RISC-V-Processor)]
|
|
|
|
|
|
|
## Acknowledgements
|
## Acknowledgements
|
