OpenCores
URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [docs/] [attrs.adoc] - Diff between revs 71 and 72

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 71 Rev 72
Line 1... Line 1...
:author: Dipl.-Ing. Stephan Nolting
:author: Dipl.-Ing. Stephan Nolting
:email: stnolting@gmail.com
:email: stnolting@gmail.com
:keywords: neorv32, risc-v, riscv, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb
:keywords: neorv32, risc-v, riscv, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb
:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
:description: A size-optimized, customizable and open-source full-scale 32-bit RISC-V soft-core CPU and SoC written in platform-independent VHDL.
:revnumber: v1.6.7
:revnumber: v1.6.8
:doctype: book
:doctype: book
:sectnums:
:sectnums:
:stem:
:stem:
:reproducible:
:reproducible:
:listing-caption: Listing
:listing-caption: Listing

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.