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The system is highly configurable and provides optional common peripherals like embedded memories,
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The system is highly configurable and provides optional common peripherals like embedded memories,
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timers, serial interfaces, general purpose IO ports and an external bus interface to connect custom IP like
|
timers, serial interfaces, general purpose IO ports and an external bus interface to connect custom IP like
|
memories, NoCs and other peripherals. On-line and in-system debugging is supported by an OpenOCD/gdb
|
memories, NoCs and other peripherals. On-line and in-system debugging is supported by an OpenOCD/gdb
|
compatible on-chip debugger accessible via JTAG.
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compatible on-chip debugger accessible via JTAG.
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|
|
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Special focus is paid on **execution safety** to provide defined and predictable behavior at any time.
|
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Therefore, the CPU ensures that all memory access are acknowledged and no invalid/malformed instructions
|
|
are executed. Whenever an unexpected situation occurs, the application code is informed via hardware exceptions.
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|
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The software framework of the processor comes with application makefiles, software libraries for all CPU
|
The software framework of the processor comes with application makefiles, software libraries for all CPU
|
and processor features, a bootloader, a runtime environment and several example programs - including a port
|
and processor features, a bootloader, a runtime environment and several example programs - including a port
|
of the CoreMark MCU benchmark and the official RISC-V architecture test suite. RISC-V GCC is used as
|
of the CoreMark MCU benchmark and the official RISC-V architecture test suite. RISC-V GCC is used as
|
default toolchain (https://github.com/stnolting/riscv-gcc-prebuilt[prebuilt toolchains are also provided]).
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default toolchain (https://github.com/stnolting/riscv-gcc-prebuilt[prebuilt toolchains are also provided]).
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...................................
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...................................
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neorv32 - Project home folder
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neorv32 - Project home folder
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│
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│
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├docs - Project documentation
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├docs - Project documentation
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│├datasheet - .adoc sources for NEORV32 data sheet
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│├datasheet - AsciiDoc sources for the NEORV32 data sheet
|
│├doxygen_build - Software framework documentation (generated by doxygen)
|
|
│├figures - Figures and logos
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│├figures - Figures and logos
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│├icons - Misc. symbols
|
│├icons - Misc. symbols
|
│├references - Data sheets and RISC-V specs.
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│├references - Data sheets and RISC-V specs.
|
│└src_adoc - AsciiDoc sources for this document
|
│└userguide - AsciiDoc sources for the NEORV32 user guide
|
│
|
│
|
├rtl - VHDL sources
|
├rtl - VHDL sources
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│├core - Core sources of the CPU & SoC
|
│├core - Core sources of the CPU & SoC
|
││└mem - SoC-internal memories (default architectures)
|
││└mem - SoC-internal memories (default architectures)
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│├processor_templates - Pre-configured SoC wrappers
|
│├processor_templates - Pre-configured SoC wrappers
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| Line 166... |
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│└...
|
│└...
|
│
|
│
|
├sim - Simulation files (see User Guide)
|
├sim - Simulation files (see User Guide)
|
│
|
│
|
└sw - Software framework
|
└sw - Software framework
|
├bootloader - Sources and scripts for the NEORV32 internal bootloader
|
├bootloader - Sources of the processor-internal bootloader
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├common - Linker script and crt0.S start-up code
|
├common - Linker script, crt0.S start-up code and central makefile
|
├example - Various example programs
|
├example - Various example programs
|
│└...
|
│└...
|
├isa-test
|
├isa-test
|
│├riscv-arch-test - RISC-V spec. compatibility test framework (submodule)
|
│├riscv-arch-test - RISC-V spec. compatibility test framework (submodule)
|
│└port-neorv32 - Port files for the official RISC-V architecture tests
|
│└port-neorv32 - Port files for the official RISC-V architecture tests
|
├ocd_firmware - source code for on-chip debugger's "park loop"
|
├ocd_firmware - Source code for on-chip debugger's "park loop"
|
├openocd - OpenOCD on-chip debugger configuration files
|
├openocd - OpenOCD on-chip debugger configuration files
|
├image_gen - Helper program to generate NEORV32 executables
|
├image_gen - Helper program to generate NEORV32 executables
|
└lib - Processor core library
|
└lib - Processor core library
|
├include - Header files (*.h)
|
├include - Header files (*.h)
|
└source - Source files (*.c)
|
└source - Source files (*.c)
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[cols="<5,>1,>1,>1,>1,>1"]
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[cols="<5,>1,>1,>1,>1,>1"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| CPU | LEs | FFs | MEM bits | DSPs | _f~max~_
|
| CPU | LEs | FFs | MEM bits | DSPs | _f~max~_
|
| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz
|
| `rv32i` | 806 | 359 | 1024 | 0 | 125 MHz
|
| `rv32i_Zicsr` | 1729 | 813 | 1024 | 0 | 124 MHz
|
| `rv32i_Zicsr_Zicntr` | 1729 | 813 | 1024 | 0 | 124 MHz
|
| `rv32im_Zicsr` | 2269 | 1055 | 1024 | 0 | 124 MHz
|
| `rv32im_Zicsr_Zicntr` | 2269 | 1055 | 1024 | 0 | 124 MHz
|
| `rv32imc_Zicsr` | 2501 | 1070 | 1024 | 0 | 124 MHz
|
| `rv32imc_Zicsr_Zicntr` | 2501 | 1070 | 1024 | 0 | 124 MHz
|
| `rv32imac_Zicsr` | 2511 | 1074 | 1024 | 0 | 124 MHz
|
| `rv32imac_Zicsr_Zicntr` | 2511 | 1074 | 1024 | 0 | 124 MHz
|
| `rv32imacu_Zicsr` | 2521 | 1079 | 1024 | 0 | 124 MHz
|
| `rv32imacu_Zicsr_Zicntr` | 2521 | 1079 | 1024 | 0 | 124 MHz
|
| `rv32imacu_Zicsr_Zifencei` | 2522 | 1079 | 1024 | 0 | 122 MHz
|
| `rv32imacu_Zicsr_Zicntr_Zifencei` | 2522 | 1079 | 1024 | 0 | 122 MHz
|
| `rv32imacu_Zicsr_Zifencei_Zfinx` | 3807 | 1731 | 1024 | 7 | 116 MHz
|
| `rv32imacu_Zicsr_Zicntr_Zifencei_Zfinx` | 3807 | 1731 | 1024 | 7 | 116 MHz
|
| `rv32imacu_Zicsr_Zifencei_Zfinx_DebugMode` | 3974 | 1815 | 1024 | 7 | 116 MHz
|
| `rv32imacu_Zicsr_Zicntr_Zifencei_Zfinx_DebugMode` | 3974 | 1815 | 1024 | 7 | 116 MHz
|
|=======================
|
|=======================
|
|
|
[NOTE]
|
[NOTE]
|
No HPM counters and no PMP regions were implemented for generating these results.
|
No HPM counters and no PMP regions were implemented for generating these results.
|
|
|
| Line 370... |
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|
|
.CoreMark results
|
.CoreMark results
|
[cols="<4,^1,^1,^1"]
|
[cols="<4,^1,^1,^1"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| CPU | CoreMark Score | CoreMarks/Mhz | Average CPI
|
| CPU | CoreMark Score | CoreMarks/MHz | Average CPI
|
| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04**
|
| _small_ (`rv32i_Zicsr`) | 33.89 | **0.3389** | **4.04**
|
| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34**
|
| _medium_ (`rv32imc_Zicsr`) | 62.50 | **0.6250** | **5.34**
|
| _performance_(`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54**
|
| _performance_(`rv32imc_Zicsr` + perf. options) | 95.23 | **0.9523** | **3.54**
|
|=======================
|
|=======================
|
|
|
