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The project aims to provide _another option_ in the RISC-V / soft-core design space with a different performance
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The project aims to provide _another option_ in the RISC-V / soft-core design space with a different performance
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vs. size trade-off and a different focus: _embrace_ concepts like documentation, platform-independence / portability,
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vs. size trade-off and a different focus: _embrace_ concepts like documentation, platform-independence / portability,
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RISC-V compatibility, _customization_ and _ease of use_. See the <<_project_key_features>> below.
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RISC-V compatibility, _customization_ and _ease of use_. See the <<_project_key_features>> below.
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Furthermore, the NEORV32 pays special focus on _execution safety_ using <<_full_virtualization>>. The CPU aims to
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provide fall-backs for _everything that could go wrong_. This includes malformed instruction words, privilege escalations
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and even memory accesses that are checked for address space holes and deterministic response times from memory-mapped
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devices. Precise exceptions allow a defined and fully-synchronized state of the CPU at every time.
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// ####################################################################################################################
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// ####################################################################################################################
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:sectnums:
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:sectnums:
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=== Project Key Features
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=== Project Key Features
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// ####################################################################################################################
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// ####################################################################################################################
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:sectnums:
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:sectnums:
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=== VHDL File Hierarchy
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=== VHDL File Hierarchy
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All necessary VHDL hardware description files are located in the project's `rtl/core folder`. The top entity
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All necessary VHDL hardware description files are located in the project's `rtl/core` folder. The top entity
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of the entire processor including all the required configuration generics is **`neorv32_top.vhd`**.
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of the entire processor including all the required configuration generics is **`neorv32_top.vhd`**.
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[IMPORTANT]
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[IMPORTANT]
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All core VHDL files from the list below have to be assigned to a new design library named **`neorv32`**. Additional
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All core VHDL files from the list below have to be assigned to a new design library named **`neorv32`**. Additional
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files, like alternative top entities, can be assigned to any library.
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files, like alternative top entities, can be assigned to any library.
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├neorv32_uart.vhd - Universal async. receiver/transmitter
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├neorv32_uart.vhd - Universal async. receiver/transmitter
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├neorv32_wdt.vhd - Watchdog timer
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├neorv32_wdt.vhd - Watchdog timer
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├neorv32_wishbone.vhd - External (Wishbone) bus interface
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├neorv32_wishbone.vhd - External (Wishbone) bus interface
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├neorv32_xirq.vhd - External interrupt controller
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├neorv32_xirq.vhd - External interrupt controller
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│
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│
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├mem/neorv32_dmem.default.vhd - _Default_ data memory (architecture-only!)
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├mem/neorv32_dmem.default.vhd - _Default_ data memory (architecture-only)
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└mem/neorv32_imem.default.vhd - _Default_ instruction memory (architecture-only!)
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└mem/neorv32_imem.default.vhd - _Default_ instruction memory (architecture-only)
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...................................
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...................................
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[NOTE]
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[NOTE]
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The processor-internal instruction and data memories (IMEM and DMEM) are split into two design files each:
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The processor-internal instruction and data memories (IMEM and DMEM) are split into two design files each:
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a plain entity definition (`neorv32_*mem.entity.vhd`) and the actual architecture definition
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a plain entity definition (`neorv32_*mem.entity.vhd`) and the actual architecture definition
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(`mem/neorv32_*mem.default.vhd`). The **default** architecture definitions from `rtl/core/mem` provide a _generic_ and
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(`mem/neorv32_*mem.default.vhd`). The `*.default.vhd` architecture definitions from `rtl/core/mem` provide a _generic_ and
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_platform independent_ memory design that (should) infers embedded memory blocks. You can replace/modify the architecture
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_platform independent_ memory design that (should) infers embedded memory blocks. You can replace/modify the architecture
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source file in order to use platform-specific features (like advanced memory resources) or to improve technology mapping
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source file in order to use platform-specific features (like advanced memory resources) or to improve technology mapping
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and/or timing.
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and/or timing.
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