| Line 32... |
Line 32... |
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
=== Processor Top Entity - Signals
|
=== Processor Top Entity - Signals
|
|
|
The following table shows all interface ports of the processor top entity (`rtl/core/neorv32_top.vhd`).
|
The following table shows signals of the processor top entity (`rtl/core/neorv32_top.vhd`).
|
The type of all signals is _std_ulogic_ or _std_ulogic_vector_, respectively.
|
The type of all signals is `std_ulogic` or `std_ulogic_vector`, respectively.
|
|
|
[TIP]
|
[IMPORTAN]
|
A wrapper for the NEORV32 Processor setup providing resolved port signals can be found in
|
All _input signals_ provide default values in case they are not explicitly assigned during instantiation.
|
`rtl/templates/processor/neorv32_ProcessorTop_stdlogic.vhd`.
|
For control signals the value `L` (weak pull-down) is used. For serial and parallel data signals
|
|
the value `U` (unknown) is used. Pulled-down signals will not cause "accidental" system crashes
|
|
since all control signals have defined level.
|
|
|
[cols="<3,^2,^2,<11"]
|
[cols="<3,^2,^2,<11"]
|
[options="header",grid="rows"]
|
[options="header",grid="rows"]
|
|=======================
|
|=======================
|
| Signal | Width | Dir. | Function
|
| Signal | Width | Dir. | Function
|
| Line 108... |
Line 110... |
| `mtime_i` | 64 | in | machine timer time (to `time[h]` CSRs) from _external MTIME_ unit if the processor-internal _MTIME_ unit is NOT implemented
|
| `mtime_i` | 64 | in | machine timer time (to `time[h]` CSRs) from _external MTIME_ unit if the processor-internal _MTIME_ unit is NOT implemented
|
| `mtime_o` | 64 | out | machine timer time from _internal MTIME_ unit if processor-internal _MTIME_ unit IS implemented
|
| `mtime_o` | 64 | out | machine timer time from _internal MTIME_ unit if processor-internal _MTIME_ unit IS implemented
|
4+^| **<<_processor_interrupts, External Interrupts>>**
|
4+^| **<<_processor_interrupts, External Interrupts>>**
|
| `xirq_i` | 32 | in | external interrupt requests (up to 32 channels)
|
| `xirq_i` | 32 | in | external interrupt requests (up to 32 channels)
|
4+^| **<<_processor_interrupts, CPU Interrupts>>**
|
4+^| **<<_processor_interrupts, CPU Interrupts>>**
|
| `nm_irq_i` | 1 | in | non-maskable interrupt
|
| `nm_irq_i` | 1 | in | non-maskable interrupt, rising-edge-triggered
|
| `mtime_irq_i` | 1 | in | machine timer interrupt13 (RISC-V)
|
| `mtime_irq_i` | 1 | in | machine timer interrupt13 (RISC-V), rising-edge-triggered
|
| `msw_irq_i` | 1 | in | machine software interrupt (RISC-V)
|
| `msw_irq_i` | 1 | in | machine software interrupt (RISC-V), rising-edge-triggered
|
| `mext_irq_i` | 1 | in | machine external interrupt (RISC-V)
|
| `mext_irq_i` | 1 | in | machine external interrupt (RISC-V), rising-edge-triggered
|
|=======================
|
|=======================
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
| Line 167... |
Line 169... |
===== _CLOCK_FREQUENCY_
|
===== _CLOCK_FREQUENCY_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CLOCK_FREQUENCY** | _natural_ | 0
|
| **CLOCK_FREQUENCY** | _natural_ | _none_
|
3+| The clock frequency of the processor's `clk_i` input port in Hertz (Hz).
|
3+| The clock frequency of the processor's `clk_i` input port in Hertz (Hz).
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _INT_BOOTLOADER_EN_
|
===== _INT_BOOTLOADER_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **INT_BOOTLOADER_EN** | _boolean_ | true
|
| **INT_BOOTLOADER_EN** | _boolean_ | false
|
3+| Implement the processor-internal boot ROM, pre-initialized with the default bootloader image when _true_.
|
3+| Implement the processor-internal boot ROM, pre-initialized with the default bootloader image when _true_.
|
This will also change the processor's boot address from the beginning of the instruction memory address space (default =
|
This will also change the processor's boot address from the beginning of the instruction memory address space (default =
|
0x00000000) to the base address of the boot ROM. See section <<_boot_configuration>> for more information.
|
0x00000000) to the base address of the boot ROM. See section <<_boot_configuration>> for more information.
|
|======
|
|======
|
|
|
| Line 375... |
Line 377... |
===== _CPU_CNT_WIDTH_
|
===== _CPU_CNT_WIDTH_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_CNT_WIDTH** | _natural_ | 0
|
| **CPU_CNT_WIDTH** | _natural_ | 64
|
3+| This generic configures the total size of the CPU's `cycle` and `instret` CSRs (low word + high word).
|
3+| This generic configures the total size of the CPU's `cycle` and `instret` CSRs (low word + high word).
|
The maximum value is 64, the minimal is 0. See
|
The maximum value is 64, the minimum value is 0. See
|
section <<_machine_counters_and_timers>> for more information. Note: Configurations with <<_cpu_cnt_width>>
|
section <<_machine_counters_and_timers>> for more information. Note: configurations with <<_cpu_cnt_width>>
|
less than 64 are not RISC-V compliant.
|
less than 64 bits do not comply to the RISC-V specs.
|
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _CPU_IPB_ENTRIES_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **CPU_IPB_ENTRIES** | _natural_ | 2
|
|
3+| This generic configures the number of entries in the CPU's instruction prefetch buffer (a FIFO).
|
|
The value has to be a power of two and has to be greater than zero.
|
|
Long linear sequences of code can benefit from an increased IPB size. For setups that use the instruction
|
|
cache (<<_icache_en>>) this generic should be set to 1.
|
|======
|
|======
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
| Line 460... |
Line 476... |
===== _MEM_INT_IMEM_EN_
|
===== _MEM_INT_IMEM_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **MEM_INT_IMEM_EN** | _boolean_ | true
|
| **MEM_INT_IMEM_EN** | _boolean_ | false
|
3+| Implement processor internal instruction memory (IMEM) when _true_.
|
3+| Implement processor internal instruction memory (IMEM) when _true_.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
| Line 489... |
Line 505... |
===== _MEM_INT_DMEM_EN_
|
===== _MEM_INT_DMEM_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **MEM_INT_DMEM_EN** | _boolean_ | true
|
| **MEM_INT_DMEM_EN** | _boolean_ | false
|
3+| Implement processor internal data memory (DMEM) when _true_.
|
3+| Implement processor internal data memory (DMEM) when _true_.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
| Line 588... |
Line 604... |
| **MEM_EXT_TIMEOUT** | _natural_ | 255
|
| **MEM_EXT_TIMEOUT** | _natural_ | 255
|
3+| Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception. Set to 0 to disable auto-timeout.
|
3+| Clock cycles after which a pending external bus access will auto-terminate and raise a bus fault exception. Set to 0 to disable auto-timeout.
|
|======
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _MEM_EXT_PIPE_MODE_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **MEM_EXT_PIPE_MODE** | _boolean_ | false
|
|
3+| Use _standard_ ("classic") Wishbone protocol for external bus when _false_; use _pipelined_ Wishbone protocol when _true_.
|
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _MEM_EXT_BIG_ENDIAN_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **MEM_EXT_BIG_ENDIAN** | _boolean_ | false
|
|
3+| Use BIG endian interface for external bus when _true_; use little endian interface when _false_.
|
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _MEM_EXT_ASYNC_RX_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **MEM_EXT_ASYNC_RX** | _boolen_ | false
|
|
3+| By default, _MEM_EXT_ASYNC_RX_ = _false_ implements a registered read-back path (RX) for incoming data in the bus interface
|
|
in order to shorten the critical path. By setting _MEM_EXT_ASYNC_RX_ = _true_ an _asynchronous_ ("direct") read-back path is
|
|
implemented reducing access latency by one cycle.
|
|
|======
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== Stream Link Interface
|
==== Stream Link Interface
|
|
|
See section <<_stream_link_interface_slink>> for more information.
|
See section <<_stream_link_interface_slink>> for more information.
|
| Line 694... |
Line 745... |
===== _IO_GPIO_EN_
|
===== _IO_GPIO_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **IO_GPIO_EN** | _boolean_ | true
|
| **IO_GPIO_EN** | _boolean_ | false
|
3+| Implement general purpose input/output port unit (GPIO) when _true_.
|
3+| Implement general purpose input/output port unit (GPIO) when _true_.
|
See section <<_general_purpose_input_and_output_port_gpio>> for more information.
|
See section <<_general_purpose_input_and_output_port_gpio>> for more information.
|
|======
|
|======
|
|
|
|
|
| Line 706... |
Line 757... |
===== _IO_MTIME_EN_
|
===== _IO_MTIME_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **IO_MTIME_EN** | _boolean_ | true
|
| **IO_MTIME_EN** | _boolean_ | false
|
3+| Implement machine system timer (MTIME) when _true_.
|
3+| Implement machine system timer (MTIME) when _true_.
|
See section <<_machine_system_timer_mtime>> for more information.
|
See section <<_machine_system_timer_mtime>> for more information.
|
|======
|
|======
|
|
|
|
|
| Line 718... |
Line 769... |
===== _IO_UART0_EN_
|
===== _IO_UART0_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **IO_UART0_EN** | _boolean_ | true
|
| **IO_UART0_EN** | _boolean_ | false
|
3+| Implement primary universal asynchronous receiver/transmitter (UART0) when _true_.
|
3+| Implement primary universal asynchronous receiver/transmitter (UART0) when _true_.
|
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
|
See section <<_primary_universal_asynchronous_receiver_and_transmitter_uart0>> for
|
more information.
|
more information.
|
|======
|
|======
|
|
|
| Line 731... |
Line 782... |
===== _IO_UART1_EN_
|
===== _IO_UART1_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **IO_UART1_EN** | _boolean_ | true
|
| **IO_UART1_EN** | _boolean_ | false
|
3+| Implement secondary universal asynchronous receiver/transmitter (UART1) when _true_.
|
3+| Implement secondary universal asynchronous receiver/transmitter (UART1) when _true_.
|
See section <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>> for more information.
|
See section <<_secondary_universal_asynchronous_receiver_and_transmitter_uart1>> for more information.
|
|======
|
|======
|
|
|
|
|
| Line 743... |
Line 794... |
===== _IO_SPI_EN_
|
===== _IO_SPI_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **IO_SPI_EN** | _boolean_ | true
|
| **IO_SPI_EN** | _boolean_ | false
|
3+| Implement serial peripheral interface controller (SPI) when _true_.
|
3+| Implement serial peripheral interface controller (SPI) when _true_.
|
See section <<_serial_peripheral_interface_controller_spi>> for more information.
|
See section <<_serial_peripheral_interface_controller_spi>> for more information.
|
|======
|
|======
|
|
|
|
|
| Line 755... |
Line 806... |
===== _IO_TWI_EN_
|
===== _IO_TWI_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **IO_TWI_EN** | _boolean_ | true
|
| **IO_TWI_EN** | _boolean_ | false
|
3+| Implement two-wire interface controller (TWI) when _true_.
|
3+| Implement two-wire interface controller (TWI) when _true_.
|
See section <<_two_wire_serial_interface_controller_twi>> for
|
See section <<_two_wire_serial_interface_controller_twi>> for
|
more information.
|
more information.
|
|======
|
|======
|
|
|
| Line 768... |
Line 819... |
===== _IO_PWM_NUM_CH_
|
===== _IO_PWM_NUM_CH_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **IO_PWM_NUM_CH** | _natural_ | 4
|
| **IO_PWM_NUM_CH** | _natural_ | 0
|
3+| Number of pulse-width modulation (PWM) channels (0..60) to implement. The PWM controller is _not_ implemented if zero.
|
3+| Number of pulse-width modulation (PWM) channels (0..60) to implement. The PWM controller is _not_ implemented if zero.
|
See section <<_pulse_width_modulation_controller_pwm>> for more information.
|
See section <<_pulse_width_modulation_controller_pwm>> for more information.
|
|======
|
|======
|
|
|
|
|
| Line 780... |
Line 831... |
===== _IO_WDT_EN_
|
===== _IO_WDT_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **IO_WDT_EN** | _boolean_ | true
|
| **IO_WDT_EN** | _boolean_ | false
|
3+| Implement watchdog timer (WDT) when _true_. See section <<_watchdog_timer_wdt>> for more
|
3+| Implement watchdog timer (WDT) when _true_. See section <<_watchdog_timer_wdt>> for more
|
information.
|
information.
|
|======
|
|======
|
|
|
|
|
| Line 848... |
Line 899... |
===== _IO_NEOLED_EN_
|
===== _IO_NEOLED_EN_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **IO_NEOLED_EN** | _boolean_ | true
|
| **IO_NEOLED_EN** | _boolean_ | false
|
3+| Implement smart LED interface (WS2812 / NeoPixel(TM)-compatible) (NEOLED) when _true_.
|
3+| Implement smart LED interface (WS2812 / NeoPixel(TM)-compatible) (NEOLED) when _true_.
|
See section <<_smart_led_interface_neoled>> for more information.
|
See section <<_smart_led_interface_neoled>> for more information.
|
|======
|
|======
|
|
|
|
|
|
:sectnums!:
|
|
===== _IO_NEOLED_TX_FIFO_
|
|
|
|
[cols="4,4,2"]
|
|
[frame="all",grid="none"]
|
|
|======
|
|
| **IO_NEOLED_TX_FIFO** | _natural_ | 1
|
|
3+| TX FIFO depth of the the NEOLED module. Minimal value is 1, maximal value is 32k, has to be a power of two.
|
|
See section <<_smart_led_interface_neoled>> for more information.
|
|
|======
|
|
|
|
|
|
|
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
=== Processor Interrupts
|
=== Processor Interrupts
|
|
|
| Line 865... |
Line 929... |
|
|
|
|
:sectnums:
|
:sectnums:
|
==== RISC-V Standard Interrupts
|
==== RISC-V Standard Interrupts
|
|
|
The processor setup features the standard RISC-V interrupt lines for "machine timer interrupt", "machine
|
The processor setup features the standard machine-level RISC-V interrupt lines for "machine timer interrupt", "machine
|
software interrupt" and "machine external interrupt". Their usage is defined by the RISC-V privileged architecture
|
software interrupt" and "machine external interrupt". Their usage is defined by the RISC-V privileged architecture
|
specifications. However, bare-metal system can also repurpose these interrupts. See CPU section
|
specifications. However, bare-metal system can also repurpose these interrupts. See CPU section
|
<<_traps_exceptions_and_interrupts>> for more information.
|
<<_traps_exceptions_and_interrupts>> for more information.
|
|
|
[cols="<3,^2,<11"]
|
[cols="<3,^2,<11"]
|
| Line 879... |
Line 943... |
| `mtime_irq_i` | 1 | Machine timer interrupt from _processor-external_ MTIME unit. This IRQ is only available if the processor-internal MTIME unit is not used (<<_io_mtime_en>> = false).
|
| `mtime_irq_i` | 1 | Machine timer interrupt from _processor-external_ MTIME unit. This IRQ is only available if the processor-internal MTIME unit is not used (<<_io_mtime_en>> = false).
|
| `msw_irq_i` | 1 | Machine software interrupt. This interrupt is used for inter-processor interrupts in multi-core systems. However, it can also be used for any custom purpose.
|
| `msw_irq_i` | 1 | Machine software interrupt. This interrupt is used for inter-processor interrupts in multi-core systems. However, it can also be used for any custom purpose.
|
| `mext_irq_i` | 1 | Machine external interrupt. This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
|
| `mext_irq_i` | 1 | Machine external interrupt. This interrupt is used for any processor-external interrupt source (like a platform interrupt controller).
|
|=======================
|
|=======================
|
|
|
[NOTE]
|
[IMPORTANT]
|
These IRQs trigger on high-level.
|
These IRQs trigger on a **rising-edge**.
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Non-Maskable Interrupt
|
==== Non-Maskable Interrupt
|
|
|
| Line 897... |
Line 961... |
|
|
The processor features a single non-maskable interrupt source via the `nm_irq_i` top
|
The processor features a single non-maskable interrupt source via the `nm_irq_i` top
|
entity signal that can be used to signal _critical system conditions_. This interrupt source _cannot_ be masked/disabled.
|
entity signal that can be used to signal _critical system conditions_. This interrupt source _cannot_ be masked/disabled.
|
See CPU section <<_traps_exceptions_and_interrupts>> for more information.
|
See CPU section <<_traps_exceptions_and_interrupts>> for more information.
|
|
|
[NOTE]
|
[IMPORTANT]
|
This IRQ triggers on high-level.
|
This IRQ triggers on a **rising-edge**.
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Platform External Interrupts
|
==== Platform External Interrupts
|
|
|
| Line 916... |
Line 980... |
The processor provides an optional interrupt controller for up to 32 user-defined external interrupts
|
The processor provides an optional interrupt controller for up to 32 user-defined external interrupts
|
(see section <<_external_interrupt_controller_xirq>>). These external IRQs are mapped to a _single_ CPU
|
(see section <<_external_interrupt_controller_xirq>>). These external IRQs are mapped to a _single_ CPU
|
fast interrupt request so a software handler is required to differentiate / prioritize these interrupts.
|
fast interrupt request so a software handler is required to differentiate / prioritize these interrupts.
|
|
|
[NOTE]
|
[NOTE]
|
The trigger for these interrupt can be defines via generics. See section
|
The trigger for these interrupt can be defined via generics. See section
|
<<_external_interrupt_controller_xirq>> for more information.
|
<<_external_interrupt_controller_xirq>> for more information.
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== NEORV32-Specific Fast Interrupt Requests
|
==== NEORV32-Specific Fast Interrupt Requests
|
| Line 947... |
Line 1011... |
| 7 | <<_two_wire_serial_interface_controller_twi,TWI>> | TWI transmission done interrupt
|
| 7 | <<_two_wire_serial_interface_controller_twi,TWI>> | TWI transmission done interrupt
|
| 8 | <<_external_interrupt_controller_xirq,XIRQ>> | External interrupt controller interrupt
|
| 8 | <<_external_interrupt_controller_xirq,XIRQ>> | External interrupt controller interrupt
|
| 9 | <<_smart_led_interface_neoled,NEOLED>> | NEOLED buffer TX empty / not full interrupt
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| 9 | <<_smart_led_interface_neoled,NEOLED>> | NEOLED buffer TX empty / not full interrupt
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| 10 | <<_stream_link_interface_slink,SLINK>> | RX data received
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| 10 | <<_stream_link_interface_slink,SLINK>> | RX data received
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| 11 | <<_stream_link_interface_slink,SLINK>> | TX data send
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| 11 | <<_stream_link_interface_slink,SLINK>> | TX data send
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| 12:15 | - | _reserved_, cannot fire
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| 12:15 | - | _reserved_, will never fire
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|=======================
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|=======================
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