| Line 24... |
Line 24... |
* _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)
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* _optional_ ring-oscillator-based true random number generator (<<_true_random_number_generator_trng,**TRNG**>>)
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* _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
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* _optional_ custom functions subsystem for custom co-processor extensions (<<_custom_functions_subsystem_cfs,**CFS**>>)
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* _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
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* _optional_ NeoPixel(TM)/WS2812-compatible smart LED interface (<<_smart_led_interface_neoled,**NEOLED**>>)
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* _optional_ external interrupt controller with up to 32 channels (<<_external_interrupt_controller_xirq,**XIRQ**>>)
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* _optional_ external interrupt controller with up to 32 channels (<<_external_interrupt_controller_xirq,**XIRQ**>>)
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* _optional_ on-chip debugger with JTAG TAP (<<_on_chip_debugger_ocd,**OCD**>>)
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* _optional_ on-chip debugger with JTAG TAP (<<_on_chip_debugger_ocd,**OCD**>>)
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* bus keeper to monitor processor-internal bus transactions (<<_internal_bus_monitor_buskeeper,**BUSKEEPER**>>)
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* system configuration information memory to check HW configuration via software (<<_system_configuration_information_memory_sysinfo,**SYSINFO**>>)
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* system configuration information memory to check HW configuration via software (<<_system_configuration_information_memory_sysinfo,**SYSINFO**>>)
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// ####################################################################################################################
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// ####################################################################################################################
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| Line 236... |
Line 237... |
See section <<_a_atomic_memory_access>>.
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See section <<_a_atomic_memory_access>>.
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|======
|
|======
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:sectnums!:
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_B_
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[cols="4,4,2"]
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[frame="all",grid="none"]
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|
|======
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| **CPU_EXTENSION_RISCV_B** | _boolean_ | false
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3+| Implement the `B` bit-manipulation sub-extension when _true_.
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See section <<_b_bit_manipulation_operations>> for more information.
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|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_C_
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===== _CPU_EXTENSION_RISCV_C_
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[cols="4,4,2"]
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[cols="4,4,2"]
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[frame="all",grid="none"]
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[frame="all",grid="none"]
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|======
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|======
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| Line 288... |
Line 301... |
See section <<_u_less_privileged_user_mode>> for more information.
|
See section <<_u_less_privileged_user_mode>> for more information.
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|======
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|======
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|
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:sectnums!:
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zbb_
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[cols="4,4,2"]
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[frame="all",grid="none"]
|
|
|======
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|
| **CPU_EXTENSION_RISCV_Zbb** | _boolean_ | false
|
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3+| Implement the `Zbb` _basic_ bit-manipulation sub-extension when _true_.
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See section <<_zbb_basic_bit_manipulation_operations>> for more information.
|
|
|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zfinx_
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===== _CPU_EXTENSION_RISCV_Zfinx_
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[cols="4,4,2"]
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[cols="4,4,2"]
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[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
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|======
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| Line 326... |
Line 327... |
See section <<_zicsr_control_and_status_register_access_privileged_architecture>> for more information.
|
See section <<_zicsr_control_and_status_register_access_privileged_architecture>> for more information.
|
|======
|
|======
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:sectnums!:
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zicntr_
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[cols="4,4,2"]
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[frame="all",grid="none"]
|
|
|======
|
|
| **CPU_EXTENSION_RISCV_Zicntr** | _boolean_ | true
|
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3+| Implement the basic CPU counter CSRs (`time[h]`, `[m]cycle[h]`, `[m]instret[h]`) when true.
|
|
Enabling this extension will set the _SYSINFO_CPU_ZICNTR_ flag in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
|
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See section <<_zicntr_cpu_base_counters>> for more information.
|
|
|======
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|
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zihpm_
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[cols="4,4,2"]
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[frame="all",grid="none"]
|
|
|======
|
|
| **CPU_EXTENSION_RISCV_Zihpm** | _boolean_ | false
|
|
3+| Implement hardware performance monitor CSRs when true.
|
|
Enabling this extension will set the _SYSINFO_CPU_ZIHPM_ flag in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
|
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See section <<_zihpm_hardware_performance_monitors>> for more information.
|
|
|======
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:sectnums!:
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===== _CPU_EXTENSION_RISCV_Zifencei_
|
===== _CPU_EXTENSION_RISCV_Zifencei_
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|
|
[cols="4,4,2"]
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[cols="4,4,2"]
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[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| Line 383... |
Line 410... |
| **FAST_SHIFT_EN** | _boolean_ | false
|
| **FAST_SHIFT_EN** | _boolean_ | false
|
3+| If this generic is set _true_ the shifter unit of the CPU's ALU is implemented as fast barrel shifter (requiring
|
3+| If this generic is set _true_ the shifter unit of the CPU's ALU is implemented as fast barrel shifter (requiring
|
more hardware resources but completing within two clock cycles). If it is set _false_, the CPU uses a serial shifter
|
more hardware resources but completing within two clock cycles). If it is set _false_, the CPU uses a serial shifter
|
that only performs a single bit shift per cycle (requiring less hardware resources, but requires up to 32 clock
|
that only performs a single bit shift per cycle (requiring less hardware resources, but requires up to 32 clock
|
cycles to complete - depending on shift amount). **Note that this option also implements barrel shifters for _all_
|
cycles to complete - depending on shift amount). **Note that this option also implements barrel shifters for _all_
|
shift-related operations of the <<_zbb_basic_bit_manipulation_operations>> extension.**
|
shift-related operations of the <<_b_bit_manipulation_operations>> extension.**
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _CPU_CNT_WIDTH_
|
===== _CPU_CNT_WIDTH_
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| Line 396... |
Line 423... |
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **CPU_CNT_WIDTH** | _natural_ | 64
|
| **CPU_CNT_WIDTH** | _natural_ | 64
|
3+| This generic configures the total size of the CPU's `[m]cycle` and `[m]instret` CSRs (low word + high word).
|
3+| This generic configures the total size of the CPU's `[m]cycle` and `[m]instret` CSRs (low word + high word).
|
The maximum value is 64, the minimum value is 0. See section <<_machine_counters_and_timers>> for more information.
|
The maximum value is 64, the minimum value is 0. See section <<_machine_counters_and_timers>> for more information.
|
|
This generic is only relevant if the `Zicntr` ISa extension is enabled (<<_cpu_extension_riscv_zicntr>>).
|
Note: configurations with <<_cpu_cnt_width>> less than 64 bits do not comply to the RISC-V specs.
|
Note: configurations with <<_cpu_cnt_width>> less than 64 bits do not comply to the RISC-V specs.
|
|======
|
|======
|
|
|
|
|
:sectnums!:
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:sectnums!:
|
| Line 448... |
Line 476... |
|
|
// ####################################################################################################################
|
// ####################################################################################################################
|
:sectnums:
|
:sectnums:
|
==== Hardware Performance Monitors (HPM)
|
==== Hardware Performance Monitors (HPM)
|
|
|
See section <<_hpm_hardware_performance_monitors>> for more information.
|
These generics allow to customize the `Zihpm` ISA extension. Note that the following generics are ignored if the
|
|
<<_cpu_extension_riscv_zihpm>> generic is _false_. See section <<_zihpm_hardware_performance_monitors>> for more information.
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _HPM_NUM_CNTS_
|
===== _HPM_NUM_CNTS_
|
|
|
[cols="4,4,2"]
|
[cols="4,4,2"]
|
[frame="all",grid="none"]
|
[frame="all",grid="none"]
|
|======
|
|======
|
| **HPM_NUM_CNTS** | _natural_ | 0
|
| **HPM_NUM_CNTS** | _natural_ | 0
|
3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero, no
|
3+| Total number of implemented hardware performance monitor counters (0..29). If this generics is zero, no
|
hardware performance monitor logic will be implemented at all. Setting <<_hpm_num_cnts>> > 0 will set the _SYSINFO_CPU_HPM_ flag
|
hardware performance monitor logic will be implemented at all.
|
in the `CPU` <<_system_configuration_information_memory_sysinfo, SYSINFO>> register.
|
|
|======
|
|======
|
|
|
|
|
:sectnums!:
|
:sectnums!:
|
===== _HPM_CNT_WIDTH_
|
===== _HPM_CNT_WIDTH_
|
| Line 1015... |
Line 1043... |
|=======================
|
|=======================
|
|
|
.Trigger type
|
.Trigger type
|
[IMPORTANT]
|
[IMPORTANT]
|
The fast interrupt request channel trigger on **high-level** and have to stay asserted until explicitly acknowledged
|
The fast interrupt request channel trigger on **high-level** and have to stay asserted until explicitly acknowledged
|
by the software (for example by writing to a specifc memory-mapped register). Hence, pending interrupts remain pending
|
by the software (for example by writing to a specific memory-mapped register). Hence, pending interrupts remain pending
|
as long as the interrupt-causing device's state fulfills it's interrupt condition(s).
|
as long as the interrupt-causing device's state fulfills it's interrupt condition(s).
|
|
|
|
|
:sectnums:
|
:sectnums:
|
==== Platform External Interrupts
|
==== Platform External Interrupts
|
| Line 1074... |
Line 1102... |
|=======================
|
|=======================
|
|
|
.Trigger type
|
.Trigger type
|
[IMPORTANT]
|
[IMPORTANT]
|
The fast interrupt request channel trigger on **high-level** and have to stay asserted until explicitly acknowledged
|
The fast interrupt request channel trigger on **high-level** and have to stay asserted until explicitly acknowledged
|
by the software (for example by writing to a specifc memory-mapped register). Hence, pending interrupts remain pending
|
by the software (for example by writing to a specific memory-mapped register). Hence, pending interrupts remain pending
|
as long as the interrupt-causing device's state fulfills it's interrupt condition(s).
|
as long as the interrupt-causing device's state fulfills it's interrupt condition(s).
|
|
|
|
|
|
|
|
|
| Line 1385... |
Line 1413... |
|
|
**Interrupts of Processor-Internal Modules**
|
**Interrupts of Processor-Internal Modules**
|
|
|
Most peripheral/IO devices provide some kind of interrupt (for example to signal available incoming data). These
|
Most peripheral/IO devices provide some kind of interrupt (for example to signal available incoming data). These
|
interrupts are entirely mapped to the CPU's <<_custom_fast_interrupt_request_lines>>. Note that all these
|
interrupts are entirely mapped to the CPU's <<_custom_fast_interrupt_request_lines>>. Note that all these
|
interrupt lines are triggered by a "one-shot" signal (hich for exactly one cycle) and _do not_ require any
|
interrupt lines are high-active and are permanently triggered until the IRQ-causing condition is resolved.
|
explicit acknowledgment.
|
|
|
|
**Nomenclature for the Peripheral / IO Devices Listing**
|
**Nomenclature for the Peripheral / IO Devices Listing**
|
|
|
Each peripheral device chapter features a register map showing accessible control and data registers of the
|
Each peripheral device chapter features a register map showing accessible control and data registers of the
|
according device including the implemented control and status bits. C-language code can directly interact with these
|
according device including the implemented control and status bits. C-language code can directly interact with these
|
| Line 1433... |
Line 1460... |
|
|
include::soc_icache.adoc[]
|
include::soc_icache.adoc[]
|
|
|
include::soc_wishbone.adoc[]
|
include::soc_wishbone.adoc[]
|
|
|
|
include::soc_buskeeper.adoc[]
|
|
|
include::soc_slink.adoc[]
|
include::soc_slink.adoc[]
|
|
|
include::soc_gpio.adoc[]
|
include::soc_gpio.adoc[]
|
|
|
include::soc_wdt.adoc[]
|
include::soc_wdt.adoc[]
|
