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| | `mtime_o` | System time output (64-bit) for SoC
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| | `mtime_o` | System time output (64-bit) for SoC
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| Configuration generics: | _IO_MTIME_EN_ | implement MTIME when _true_
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| Configuration generics: | _IO_MTIME_EN_ | implement MTIME when _true_
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| CPU interrupts: | `MTI` | machine timer interrupt (see <<_processor_interrupts>>)
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| CPU interrupts: | `MTI` | machine timer interrupt (see <<_processor_interrupts>>)
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|=======================
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|=======================
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**Theory of Operation**
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The MTIME module implements the memory-mapped MTIME machine timer from the official RISC-V
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specifications. This module features a 64-bit system timer incrementing with the primary processor clock.
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Besides accessing the MTIME register via memory operation the current system time can also be obtained using
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the `time[h]` CSRs. Furthermore, the current system time is made available for processor-external
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usage via the top's `mtime_o` signal.
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The MTIME machine system timer implements the memory-mapped MTIME timer from the official RISC-V
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The 64-bit system time can be accessed via the `TIME_LO` and `TIME_HI` memory-mapped registers (read/write) and also via
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specifications. This unit features a 64-bit system timer incremented with the primary processor clock.
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the CPU's `time[h]` CSRs (read-only). A 64-bit time compare register - accessible via the memory-mapped `TIMECMP_LO` and `TIMECMP_HI`
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The current system time can also be obtained using the `time[h]` CSRs and is made available for processor-external
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registers - is used to configure the CPU's MTI (machine timer interrupt). The interrupt is triggered
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use via the top's `mtime_o` signal.
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whenever `TIME` (high & low part) is greater than or equal to `TIMECMP` (high & low part).
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The interrupt remain active (=pending) until `TIME` becomes less `TIMECMP` again (either by modifying `TIME` or `TIMECMP`).
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[NOTE]
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[NOTE]
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If the processor-internal **MTIME unit is NOT implemented**, the top's `mtime_i` input signal is used to update the `time[h]` CSRs
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If the processor-internal **MTIME module is NOT implemented**, the top's `mtime_i` input signal is used to update the `time[h]` CSRs
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and the `MTI` machine timer CPU interrupt (`MTI`) is directly connected to the top's `mtime_irq_i` input.
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and the `MTI` machine timer CPU interrupt (`MTI`) is directly connected to the top's `mtime_irq_i` input. The `mtime_o` signal
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is hardwired to zero in this case.
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The 64-bit system time can be accessed via the `TIME_LO` and `TIME_HI` memory-mapped registers (read/write) and also via
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the CPU's `time[h]` CSRs (read-only). A 64-bit time compare register - accessible via memory-mapped `TIMECMP_LO` and `TIMECMP_HI`
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registers - is used to configure an interrupt to the CPU. The interrupt is triggered
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whenever `TIME` (high & low part) >= `TIMECMP` (high & low part) and is directly forwarded to the CPU's `MTI` interrupt.
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The interrupt remain active (=pending) until `TIME` < `TIMECMP` (either by modifying `TIME` or `TIMECMP`).
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.MTIME register map (`struct NEORV32_MTIME`)
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.MTIME register map (`struct NEORV32_MTIME`)
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[cols="<3,<3,^1,^1,<6"]
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[cols="<3,<3,^1,^1,<6"]
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[options="header",grid="all"]
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[options="header",grid="all"]
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|=======================
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|=======================
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