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Line 77... |
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[WARNING]
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[WARNING]
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The NEORV32 processor ensures that _any_ CPU access to memory-mapped devices (including the SLINK module)
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The NEORV32 processor ensures that _any_ CPU access to memory-mapped devices (including the SLINK module)
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will **time out** after a certain number of cycles (see section <<_bus_interface>>).
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will **time out** after a certain number of cycles (see section <<_bus_interface>>).
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Hence, blocking access to a stream link that does not complete within a certain amount of cycles will
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Hence, blocking access to a stream link that does not complete within a certain amount of cycles will
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raise a _store bus access exception_ when writing a _full_ TX link or a _load bus access exception_ when reading
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raise a _store bus access exception_ when writing to a _full_ TX link's FIFO or a _load bus access exception_
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from an _empty_ RX link. Hence, this concept should only be used when evaluating the half-full FIFO condition
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when reading from an _empty_ RX 's FIFO. Hence, this concept should only be used when evaluating the half-full
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(for example via the SLINK interrupts) before actual accessing links.
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FIFO condition (for example via the SLINK interrupts) before actual accessing links.
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[NOTE]
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There is no RX FIFO overflow mechanism available yet.
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**Non-Blocking Link Access**
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**Non-Blocking Link Access**
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For a non-blocking link access concept, the FIFO status flags in `STATUS` need to be checked _before_
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For a non-blocking link access concept, the FIFO status flags in `STATUS` need to be checked _before_
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Line 119... |
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[TIP]
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[TIP]
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The SLINK handshake protocol is compatible with the https://developer.arm.com/documentation/ihi0051/a/Introduction/About-the-AXI4-Stream-protocol[AXI4-Stream] base protocol.
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The SLINK handshake protocol is compatible with the https://developer.arm.com/documentation/ihi0051/a/Introduction/About-the-AXI4-Stream-protocol[AXI4-Stream] base protocol.
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**Interrupts**
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**SLINK Interrupts**
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The stream interface provides two independent interrupts that are _globally_ driven by the RX and TX link's
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The stream interface provides two independent interrupts that are _globally_ driven by the RX and TX link's
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FIFO fill level status. Each RX and TX link provides an individual interrupt enable flag and an individual
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FIFO fill level status. Each RX and TX link provides an individual interrupt enable flag and an individual
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interrupt type flag that allows to configure interrupts only for certain (or all) links and for application-
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interrupt type flag that allows to configure interrupts only for certain (or all) links and for application-
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specific interrupt conditions. The interrupt configuration is done using the `NEORV32_SLINK.IRQ` register.
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specific FIFO conditions. The interrupt configuration is done using the `NEORV32_SLINK.IRQ` register.
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Any interrupt can only become pending if the SLINK module is enabled at all.
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Any interrupt can only become pending if the SLINK module is enabled at all.
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[NOTE]
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There is no RX FIFO overflow mechanism available yet.
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The current FIFO fill-level of a specific **RX link** can only raise an interrupt request if it's interrupt enable flag
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The current FIFO fill-level of a specific **RX link** can only raise an interrupt request if it's interrupt enable flag
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_SLINK_IRQ_RX_EN_ is set. Vice versa, the current FIFO fill-level of a specific **TX link** can only raise an interrupt
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_SLINK_IRQ_RX_EN_ is set. Vice versa, the current FIFO fill-level of a specific **TX link** can only raise an interrupt
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request if it's interrupt enable flag _SLINK_IRQ_TX_EN_ is set.
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request if it's interrupt enable flag _SLINK_IRQ_TX_EN_ is set.
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The **RX link's** _SLINK_IRQ_RX_MODE_ flags define the FIFO fill-level condition for raising an RX interrupt request:
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The **RX link's** _SLINK_IRQ_RX_MODE_ flags define the FIFO fill-level condition for raising an RX interrupt request:
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* If a link's interrupt mode flag is `1` an IRQ is generated when the link's FIFO is _not empty_ ("RX data available").
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* If a link's interrupt mode flag is `1` an IRQ is generated when the link's FIFO _becomes_ not empty ("RX data available").
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* If a link's interrupt mode flag is `0` an IRQ is generated when the link's FIFO is _at least half-full_ ("time to get data from RX FIFO to prevent overflow").
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* If a link's interrupt mode flag is `0` an IRQ is generated when the link's FIFO _becomes_ at least half-full ("time to get data from RX FIFO to prevent overflow").
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The **TX link's** _SLINK_IRQ_TX_MODE_ flags define the FIFO fill-level condition for raising an TX interrupt request:
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The **TX link's** _SLINK_IRQ_TX_MODE_ flags define the FIFO fill-level condition for raising an TX interrupt request:
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* If a link's interrupt mode flag is `1` an IRQ is generated when the link's FIFO is _not full_ ("space left in FIFO for new TX data").
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* If a link's interrupt mode flag is `1` an IRQ is generated when the link's FIFO _becomes_ not full ("space left in FIFO for new TX data").
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* If a link's interrupt mode flag is `0` an IRQ is generated when the link's FIFO is _less than half-full_ ("SW can send _SLINK_TX_FIFO_/2 data words without checking any flags").
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* If a link's interrupt mode flag is `0` an IRQ is generated when the link's FIFO _becomes_ less than half-full ("SW can send _SLINK_TX_FIFO_/2 data words without checking any flags").
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[NOTE]
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[IMPORTANT]
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If _SLINK_RX_FIFO_ is 1 the _SLINK_IRQ_RX_MODE_ bits are hardwired to one.
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The interrupt configuration register `NEORV32_SLINK.IRQ` should we written _before_ the SLINK
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If _SLINK_TX_FIFO_ is 1 the _SLINK_IRQ_TX_MODE_ bits are hardwired to one.
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module is actually enabled.
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[NOTE]
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[NOTE]
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There is no RX FIFO overflow mechanism available yet.
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If _SLINK_RX_FIFO_ is 1 all _SLINK_IRQ_RX_MODE_ bits are hardwired to one.
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If _SLINK_TX_FIFO_ is 1 all _SLINK_IRQ_TX_MODE_ bits are hardwired to one.
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If _any_ configured interrupt condition is fulfilled, the according global SLINK RX / SLINK TX CPU
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A **pending RX interrupt** request is cleared by any of the following operations:
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interrupt becomes pending.
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* read access to any `NEORV32_SLINK.DATA` (for example to read incoming data)
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If the interrupt enable flags of several links are set, the interrupt service handler has to evaluate the SLINK
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* write access to `NEORV32_SLINK.CTRL`
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status register is order to detect which link(s) caused the interrupt.
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* disabling the SLINK module
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A **pending TX interrupt** request is cleared by any of the following operations:
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* write access any `NEORV32_SLINK.DATA` (for example to send more data)
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* write access to `NEORV32_SLINK.CTRL`
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* disabling the SLINK module
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[NOTE]
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[TIP]
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If the programmed interrupt condition is fulfilled, the corresponding IRQ will become _pending_ until
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A dummy write to to the control register (i.e. `NEORV32_SLINK.DATA = NEORV32_SLINK.DATA`)
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the causing interrupt conditions is resolved (for example by reading data from the according RX FIFO).
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can be executed to acknowledge any interrupt.
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.SLINK register map (`struct NEORV32_SLINK`)
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.SLINK register map (`struct NEORV32_SLINK`)
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[cols="^4,<5,^2,^2,<14"]
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[cols="^4,<5,^2,^2,<14"]
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[options="header",grid="all"]
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[options="header",grid="all"]
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| Line 166... |
Line 178... |
<| `11:8` _SLINK_CTRL_RX_FIFO_S3_ : _SLINK_CTRL_RX_FIFO_S0_ ^| r/- <| RX links FIFO depth, log2 of_SLINK_RX_FIFO_ generic
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<| `11:8` _SLINK_CTRL_RX_FIFO_S3_ : _SLINK_CTRL_RX_FIFO_S0_ ^| r/- <| RX links FIFO depth, log2 of_SLINK_RX_FIFO_ generic
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<| `7:4` _SLINK_CTRL_TX_NUM3_ : _SLINK_CTRL_TX_NUM0_ ^| r/- <| Number of implemented TX links
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<| `7:4` _SLINK_CTRL_TX_NUM3_ : _SLINK_CTRL_TX_NUM0_ ^| r/- <| Number of implemented TX links
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<| `3:0` _SLINK_CTRL_RX_NUM3_ : _SLINK_CTRL_RX_NUM0_ ^| r/- <| Number of implemented RX links
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<| `3:0` _SLINK_CTRL_RX_NUM3_ : _SLINK_CTRL_RX_NUM0_ ^| r/- <| Number of implemented RX links
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| `0xfffffec4` | - |`31:0` | r/- | _reserved_
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| `0xfffffec4` | - |`31:0` | r/- | _reserved_
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.4+<| `0xfffffec8` .4+<| `NEORV32_SLINK.IRQ` <|`31:24` _SLINK_IRQ_RX_EN_MSB_ : _SLINK_IRQ_RX_EN_LSB_ ^| r/w <| RX interrupt enable for link 7..0
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.4+<| `0xfffffec8` .4+<| `NEORV32_SLINK.IRQ` <|`31:24` _SLINK_IRQ_RX_EN_MSB_ : _SLINK_IRQ_RX_EN_LSB_ ^| r/w <| RX interrupt enable for link 7..0
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<|`23:16` _SLINK_IRQ_RX_MODE_MSB_ : _SLINK_IRQ_RX_MODE_LSB_ ^| r/w <| RX IRQ mode for link 7..0: `0` = FIFO at least half-full; `1` = FIFO not empty
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<|`23:16` _SLINK_IRQ_RX_MODE_MSB_ : _SLINK_IRQ_RX_MODE_LSB_ ^| r/w <| RX IRQ mode for link 7..0: `0` = FIFO rises above half-full; `1` = FIFO not empty
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<|`15:8` _SLINK_IRQ_TX_EN_MSB_ : _SLINK_IRQ_TX_EN_LSB_ ^| r/w <| TX interrupt enable for link 7..0
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<|`15:8` _SLINK_IRQ_TX_EN_MSB_ : _SLINK_IRQ_TX_EN_LSB_ ^| r/w <| TX interrupt enable for link 7..0
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<|`7:0` _SLINK_IRQ_TX_MODE_MSB_ : _SLINK_IRQ_TX_MODE_LSB_ ^| r/w <| TX IRQ mode for link 7..0: `0` = FIFO less than half-full; `1` = FIFO not full
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<|`7:0` _SLINK_IRQ_TX_MODE_MSB_ : _SLINK_IRQ_TX_MODE_LSB_ ^| r/w <| TX IRQ mode for link 7..0: `0` = FIFO falls below half-full; `1` = FIFO not full
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| `0xfffffeec` | - |`31:0` | r/- | _reserved_
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| `0xfffffeec` | - |`31:0` | r/- | _reserved_
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.4+<| `0xfffffed0` .4+<| `NEORV32_SLINK.STATUS` <| `31:24` _SLINK_STATUS_TX7_HALF_ : _SLINK_STATUS_TX0_HALF_ ^| r/- <| TX link 7..0 FIFO fill level is >= half-full
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.4+<| `0xfffffed0` .4+<| `NEORV32_SLINK.STATUS` <| `31:24` _SLINK_STATUS_TX7_HALF_ : _SLINK_STATUS_TX0_HALF_ ^| r/- <| TX link 7..0 FIFO fill level is >= half-full
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<| `23:16` _SLINK_STATUS_RX7_HALF_ : _SLINK_STATUS_RX0_HALF_ ^| r/- <| RX link 7..0 FIFO fill level is >= half-full
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<| `23:16` _SLINK_STATUS_RX7_HALF_ : _SLINK_STATUS_RX0_HALF_ ^| r/- <| RX link 7..0 FIFO fill level is >= half-full
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<| `15:8` _SLINK_STATUS_TX7_FREE_ : _SLINK_STATUS_TX0_FREE_ ^| r/- <| At least one free TX FIFO entry available for link 7..0
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<| `15:8` _SLINK_STATUS_TX7_FREE_ : _SLINK_STATUS_TX0_FREE_ ^| r/- <| At least one free TX FIFO entry available for link 7..0
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<| `7:0` _SLINK_STATUS_RX7_AVAIL_ : _SLINK_STATUS_RX0_AVAIL_ ^| r/- <| At least one data word in RX FIFO available for link 7..0
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<| `7:0` _SLINK_STATUS_RX7_AVAIL_ : _SLINK_STATUS_RX0_AVAIL_ ^| r/- <| At least one data word in RX FIFO available for link 7..0
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