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SPI is a synchronous serial transmission interface for fast on-board communications.
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SPI is a synchronous serial transmission interface for fast on-board communications.
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The NEORV32 SPI transceiver supports 8-, 16-, 24- and 32-bit wide transmissions.
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The NEORV32 SPI transceiver supports 8-, 16-, 24- and 32-bit wide transmissions.
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The unit provides 8 dedicated chip select signals via the top entity's `spi_csn_o` signal, which are
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The unit provides 8 dedicated chip select signals via the top entity's `spi_csn_o` signal, which are
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directly controlled by the SPI module (no additional GPIO required).
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directly controlled by the SPI module (no additional GPIO required).
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[NOTE]
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The NEORV32 SPI module only supports _host mode_. Transmission are initiated only by the processor's SPI module
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(and not by an external SPI module).
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The SPI unit is enabled by setting the _SPI_CTRL_EN_ bit in the `CTRL` control register. No transfer can be initiated
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The SPI unit is enabled by setting the _SPI_CTRL_EN_ bit in the `CTRL` control register. No transfer can be initiated
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and no interrupt request will be triggered if this bit is cleared. Furthermore, a transfer being in process
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and no interrupt request will be triggered if this bit is cleared. Furthermore, a transfer being in process
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can be terminated at any time by clearing this bit.
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can be terminated at any time by clearing this bit.
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[IMPORTANT]
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Changes to the `CTRL` control register should be made only when the SPI module is idle as they directly effect
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transmissions being in-progress.
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[TIP]
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A transmission can be terminated at any time by disabling the SPI module
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by clearing the _SPI_CTRL_EN_ control register bit.
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The data quantity to be transferred within a single transmission is defined via the _SPI_CTRL_SIZEx_ bits.
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The data quantity to be transferred within a single transmission is defined via the _SPI_CTRL_SIZEx_ bits.
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The SPI module supports 8-bit (`00`), 16-bit (`01`), 24-
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The SPI module supports 8-bit (`00`), 16-bit (`01`), 24-bit (`10`) and 32-bit (`11`) transfers.
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bit (`10`) and 32-bit (`11`) transfers.
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A transmission is started when writing data to the `DATA` register. The data must be LSB-aligned. So if
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A transmission is started when writing data to the `DATA` register. The data must be LSB-aligned. So if
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the SPI transceiver is configured for less than 32-bit transfers data quantity, the transmit data must be placed
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the SPI transceiver is configured for less than 32-bit transfers data quantity, the transmit data must be placed
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into the lowest 8/16/24 bit of `DATA`. Vice versa, the received data is also always LSB-aligned. Application
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into the lowest 8/16/24 bit of `DATA`. Vice versa, the received data is also always LSB-aligned. Application
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software should only actually process the amount of bits that were configured using _SPI_CTRL_SIZEx_ when
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software should only actually process the amount of bits that were configured using _SPI_CTRL_SIZEx_ when
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reading `DATA`.
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reading `DATA`.
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The SPI controller features 8 dedicated chip-select lines. These lines are controlled via the control register's
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[NOTE]
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_SPI_CTRL_CSx_ bits. When a specific _SPI_CTRL_CSx_ bit is **set**, the according chip-select line `spi_csn_o(x)`
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The NEORV32 SPI module only support MSB-first mode. Data can be reversed before writing `DATA` (for TX) / after
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goes **low** (low-active chip-select lines).
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reading `DATA` (for RX) to implement LSB-first transmissions. Note that in both cases data in ` DATA` still
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needs to be LSB-aligned.
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[IMPORTANT]
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Changes to the `CTRL` control register should be made only when the SPI module is idle as they directly effect
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transmissions being in-progress.
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[TIP]
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[TIP]
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The actual transmission length is left to the user: after asserting chip-select an arbitrary amount of
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The actual transmission length is left to the user: after asserting chip-select an arbitrary amount of
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transmission with arbitrary data quantity (_SPI_CTRL_SIZEx_) can be made before de-asserting chip-select again.
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transmission with arbitrary data quantity (_SPI_CTRL_SIZEx_) can be made before de-asserting chip-select again.
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[NOTE]
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The SPI controller features 8 dedicated chip-select lines. These lines are controlled via the control register's
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The NEORV32 SPI module only supports _host mode_. Transmission are initiated only by the processor's SPI module
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_SPI_CTRL_CSx_ bits. When a specific _SPI_CTRL_CSx_ bit is **set**, the according chip-select line `spi_csn_o(x)`
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(and not by an external SPI module).
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goes **low** (low-active chip-select lines).
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[NOTE]
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[TIP]
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The NEORV32 SPI module only support MSB-first mode. Data can be reversed before writing `DATA` (for TX) / after
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The dedicated SPI chip-select signals can be seen as _general purpose_ outputs. These are intended to control
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reading `DATA` (for RX) to provide LSB-first transmissions.
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the accessed device's chip-select signal but can also be use for controlling other shift register signals
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(like data strobe or output-enables).
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**SPI Clock Configuration**
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**SPI Clock Configuration**
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The SPI module supports all _standard SPI clock modes_ (0, 1, 2, 3), which is via the two control register bits
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The SPI module supports all _standard SPI clock modes_ (0, 1, 2, 3), which is via the two control register bits
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