| Line 102... |
Line 102... |
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_**f~SPI~**_ = _f~main~[Hz]_ / (2 * `clock_prescaler`)
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_**f~SPI~**_ = _f~main~[Hz]_ / (2 * `clock_prescaler`)
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Hence, the maximum SPI clock is f~main~ / 4.
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Hence, the maximum SPI clock is f~main~ / 4.
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.High-Speed SPI mode
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[TIP]
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The module provides a "high-speed" SPI mode. In this mode the clock prescaler configuration (SPI_CTRL_PRSCx) is ignored
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and the SPI clock operates at f~main~ / 2 (half of the processor's main clock). High speed SPI mode is enabled by setting
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the control register's _SPI_CTRL_HIGHSPEED_ bit.
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**SPI Interrupt**
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**SPI Interrupt**
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The SPI module provides a single interrupt to signal "transmission done" to the CPU. Whenever the SPI
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The SPI module provides a single interrupt to signal "transmission done" to the CPU. Whenever the SPI
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module completes the current transfer operation, the interrupt is triggered and has to be explicitly cleared again
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module completes the current transfer operation, the interrupt is triggered and has to be explicitly cleared again
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| Line 115... |
Line 121... |
.SPI register map (`struct NEORV32_SPI`)
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.SPI register map (`struct NEORV32_SPI`)
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[cols="<2,<2,<4,^1,<7"]
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[cols="<2,<2,<4,^1,<7"]
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[options="header",grid="all"]
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[options="header",grid="all"]
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|=======================
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|=======================
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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| Address | Name [C] | Bit(s), Name [C] | R/W | Function
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.18+<| `0xffffffa8` .18+<| `NEORV32_SPI.CTRL` <|`0` _SPI_CTRL_CS0_ ^| r/w .8+<| Direct chip-select 0..7; setting `spi_csn_o(x)` low when set
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.19+<| `0xffffffa8` .19+<| `NEORV32_SPI.CTRL` <|`0` _SPI_CTRL_CS0_ ^| r/w .8+<| Direct chip-select 0..7; setting `spi_csn_o(x)` low when set
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<|`1` _SPI_CTRL_CS1_ ^| r/w
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<|`1` _SPI_CTRL_CS1_ ^| r/w
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<|`2` _SPI_CTRL_CS2_ ^| r/w
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<|`2` _SPI_CTRL_CS2_ ^| r/w
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<|`3` _SPI_CTRL_CS3_ ^| r/w
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<|`3` _SPI_CTRL_CS3_ ^| r/w
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<|`4` _SPI_CTRL_CS4_ ^| r/w
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<|`4` _SPI_CTRL_CS4_ ^| r/w
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<|`5` _SPI_CTRL_CS5_ ^| r/w
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<|`5` _SPI_CTRL_CS5_ ^| r/w
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| Line 131... |
Line 137... |
<|`11` _SPI_CTRL_PRSC1_ ^| r/w
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<|`11` _SPI_CTRL_PRSC1_ ^| r/w
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<|`12` _SPI_CTRL_PRSC2_ ^| r/w
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<|`12` _SPI_CTRL_PRSC2_ ^| r/w
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<|`13` _SPI_CTRL_SIZE0_ ^| r/w .2+<| transfer size (`00`=8-bit, `01`=16-bit, `10`=24-bit, `11`=32-bit)
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<|`13` _SPI_CTRL_SIZE0_ ^| r/w .2+<| transfer size (`00`=8-bit, `01`=16-bit, `10`=24-bit, `11`=32-bit)
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<|`14` _SPI_CTRL_SIZE1_ ^| r/w
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<|`14` _SPI_CTRL_SIZE1_ ^| r/w
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<|`15` _SPI_CTRL_CPOL_ ^| r/w <| clock polarity
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<|`15` _SPI_CTRL_CPOL_ ^| r/w <| clock polarity
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<|`16` .. `30` ^| r/- <| _reserved, read as zero
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<|`16` _SPI_CTRL_HIGHSPEED_ ^| r/w <| enable SPI high-speed mode (ignoring _SPI_CTRL_PRSC_)
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<|`17:30` ^| r/- <| _reserved, read as zero
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<|`31` _SPI_CTRL_BUSY_ ^| r/- <| transmission in progress when set
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<|`31` _SPI_CTRL_BUSY_ ^| r/- <| transmission in progress when set
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| `0xffffffac` | `NEORV32_SPI.DATA` |`31:0` | r/w | receive/transmit data, LSB-aligned
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| `0xffffffac` | `NEORV32_SPI.DATA` |`31:0` | r/w | receive/transmit data, LSB-aligned
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|=======================
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|=======================
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